Device design, fabrication and characterization of 0.8 /spl mu/m CMOS technology

Abstract

An intensive study has been conducted for the development of the MIMOS 0.8 /spl mu/m CMOS technology. Issues such as device design and characterization have been given much consideration. NMOS and PMOS transistors have been designed from basic concepts and using simulation tools such as TSUPREM-4 and MEDICI. Device design constraints such as threshold voltage variation, off-state leakage current and drain-induced barrier lowering (DIBL) effects have been seriously examined to improve device performance. Furthermore, performance criteria such as drive current capability have also been examined. Extraction of device characteristics from silicon has been performed on a test chip. Based on experimental results, numerous I-V plots are presented and the data are discussed in terms of output and transfer characteristics and surface DIBL leakage current.