Influence of gate-source/drain overlap on FeFETs

Abstract

The influences of gate-source/drain overlap on ferroelectric field-effect transistors (FeFETs) are investigated with various gate-source/drain overlap lengths (L_ov’s) and doping concentrations of the gate-source/drain overlap region (D_ov’s). In contrast to conventional metal-ferroelectric-insulator-semiconductor (MFIS) FeFETs, a metal layer between a ferroelectric and an insulator layer allows overlap capacitance to affect the entire ferroelectric layer in metal-ferroelectric-metal–insulator-semiconductor (MFMIS) FeFETs. As L_ov and D_ov increase, the effective channel length of both FeFETs decreases. In the case of MFMIS FeFETs, the gate-to-source/drain overlap capacitance (C_ov,gate-S/D) increases, leading to a larger voltage drop across the ferroelectric layer. According to the simulation results, MFMIS FeFETs show a wider memory window (MW) and larger sensing margin than MFIS FeFETs.