Circuit Implementation of Modular Adders in Custom CMOS VLSI and FPGA

Q4 Engineering Russian Microelectronics Pub Date : 2024-02-15 DOI:10.1134/s1063739723070053

P. N. Bibilo, N. A. Kirienko

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Abstract—

Modular arithmetic is often used to create high-speed computing systems based on both custom digital VLSI circuits and field-programmable gate arrays (FPGAs). The problems of hardware implementation of neural networks based on modular arithmetic calculations are relevant today. In this study, the problem of implementing modular adders in the library for designing custom CMOS VLSI systems and FPGAs is considered. Systems of both fully and incompletely defined (partial) Boolean functions, as well as algorithmic descriptions in the VHDL language, are used as the initial descriptions of modular adders. Logical optimization preceding logical synthesis is carried out in the class of disjunctive normal forms, Reed–Muller polynomial representations, and representations of Boolean function systems by binary decision diagrams. Nine experiments are carried out on the efficiency of applying logic optimization in the circuit implementation of modular adders in the library for designing custom CMOS VLSI circuits and FPGAs. The obtained circuits of modular adders for CMOS VLSI systems are estimated by area (total number of transistors), delay, and power consumption; and for FPGAs, by the number of programmable logic elements and power consumption. The experimental results show that the use of partial function models and preliminary logical optimization based on binary decision diagrams makes it possible to obtain modular adders characterized by lower delay values. Algorithmic VHDL models make it possible to obtain CMOS modular adder circuits with a smaller area and lower power consumption.

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定制 CMOS VLSI 和 FPGA 模块化加法器的电路实现

摘要-模块化算术通常用于创建基于定制数字 VLSI 电路和现场可编程门阵列 (FPGA) 的高速计算系统。基于模块化算术计算的神经网络的硬件实现问题在今天仍然具有现实意义。本研究考虑了在设计定制 CMOS VLSI 系统和 FPGA 的库中实现模块加法器的问题。完全和不完全定义的（部分）布尔函数系统以及 VHDL 语言中的算法描述被用作模块加法器的初始描述。在逻辑综合之前的逻辑优化是在析取正则表达式、里德-穆勒多项式表示法和二进制决策图的布尔函数系统表示法中进行的。在定制 CMOS VLSI 电路和 FPGA 设计库中的模块加法器电路实现中应用逻辑优化的效率进行了九次实验。对于 CMOS VLSI 系统，所获得的模块加法器电路按面积（晶体管总数）、延迟和功耗进行了估算；对于 FPGA，则按可编程逻辑元件的数量和功耗进行了估算。实验结果表明，使用部分函数模型和基于二进制决策图的初步逻辑优化，可以获得延迟值较低的模块加法器。算法 VHDL 模型使得 CMOS 模块加法器电路具有更小的面积和更低的功耗。

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来源期刊

Russian Microelectronics Materials Science-Materials Chemistry

CiteScore

0.70

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0.00%

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期刊介绍： Russian Microelectronics covers physical, technological, and some VLSI and ULSI circuit-technical aspects of microelectronics and nanoelectronics; it informs the reader of new trends in submicron optical, x-ray, electron, and ion-beam lithography technology; dry processing techniques, etching, doping; and deposition and planarization technology. Significant space is devoted to problems arising in the application of proton, electron, and ion beams, plasma, etc. Consideration is given to new equipment, including cluster tools and control in situ and submicron CMOS, bipolar, and BICMOS technologies. The journal publishes papers addressing problems of molecular beam epitaxy and related processes; heterojunction devices and integrated circuits; the technology and devices of nanoelectronics; and the fabrication of nanometer scale devices, including new device structures, quantum-effect devices, and superconducting devices. The reader will find papers containing news of the diagnostics of surfaces and microelectronic structures, the modeling of technological processes and devices in micro- and nanoelectronics, including nanotransistors, and solid state qubits.