Process optimization of titanium self-aligned silicide formation through evaluation of sheet resistance by design of experiment methodology

Abstract

A low-resistivity titanium silicide (TiSi₂) is crucial as a gate and source/drain material in microelectronic device fabrication, offering notable properties to enhance device performance. This study aims to experimentally determine the optimum process parameters, including arsenic doping dosage, titanium thickness, and two-step rapid thermal process (RTP) temperature, for the sheet resistance of titanium self-aligned silicide process using a design of experiment methodology. The results demonstrate that both the thickness of the titanium and the temperature of the RTP play crucial roles in determining the sheet resistance of TiSi₂. Statistical analysis reveals that increasing the titanium thickness or the temperature of the first-step RTP (RTP-1) could reduce the sheet resistance. Additionally, an optimal second-step RTP (RTP-2) temperature is critical to yield low-resistivity TiSi₂ by completely converting C49- to C54-phase. The optimum process conditions for obtaining low sheet resistance are a titanium thickness of 32–35 nm, RTP-1 temperature of 720–750 °C for 75 s, and RTP-2 temperature of 860 °C for 20 s. Moreover, surface amorphization of the polysilicon by arsenic ion implantation before the deposition of Ti/TiN films also plays a crucial role in the formation of C54-TiSi₂. The lowest sheet resistance achieved was 3.91 Ω/sq with an arsenic dosage of 1 × 10¹⁴ cm⁻². The optimum condition was adopted for forming a submicron polysilicon gate, providing a promising approach for designing the process parameters for titanium self-aligned silicide formation to achieve low resistance in nanoscale electronic devices.