From Multipliers to Integrators: A Survey of Stochastic Computing Primitives

Abstract

Stochastic Computing (SC) has the potential to dramatically improve important nanoscale circuit metrics, including area and power dissipation, for implementing complex digital computing systems, such as large neural networks, filters, or decoders, among others. This paper reviews the state-of-the-art design of important SC building blocks covering both arithmetic circuits, including multipliers, adders, and dividers, and finite state machines (FSMs) that are needed for numerical integration, accumulation, and activation functions in neural networks. For arithmetic circuits, we review newly proposed schemes, such as Delta Sigma Modulator-based dividers providing accurate and low latency computation, as well as design considerations by which the degree of correlation/decorrelation can be efficiently handled at the arithmetic circuit level. As for complex sequential circuits, we review classical stochastic FSM schemes as well as new designs using the recently-proposed dynamic SC to reduce the length of a stochastic sequence to obtain computation results. These stochastic circuits are compared to traditional implementations in terms of efficiency and delay for various levels of accuracy to illustrate the ranges of values for which SC provides significant performance benefits.