Degradation and Reliability Modeling of EM Robustness of Voltage Regulators Based on ADT: An Approach and a Case Study

IF 2.5 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Device and Materials Reliability Pub Date : 2023-12-07 DOI:10.1109/TDMR.2023.3340426
Jaber Al Rashid;Mohsen Koohestani;Laurent Saintis;Mihaela Barreau
{"title":"Degradation and Reliability Modeling of EM Robustness of Voltage Regulators Based on ADT: An Approach and a Case Study","authors":"Jaber Al Rashid;Mohsen Koohestani;Laurent Saintis;Mihaela Barreau","doi":"10.1109/TDMR.2023.3340426","DOIUrl":null,"url":null,"abstract":"This paper presents an approach to develop degradation and reliability models of analog integrated circuit (IC) voltage regulators based on the long-term evolution of the electromagnetic compatibility (EMC) performance degradation due to the stress time-dependent accelerated degradation test (ADT). The ADT plan is designed and conducted on six samples of both UA78L05 and L78L05 ICs placed inside a climatic chamber combining both the thermal step-stress (i.e., 70-110 °C) and constant electrical overstress (i.e., 9 and 12 V) conditions for a total stress duration of 950 hours. All the selected UA78L05 and L78L05 samples are subjected to the direct power injection (DPI) measurement test under nominal conditions in order to characterize their immunity to electromagnetic interference (EMI). The statistical degradation data (i.e., the average injected power) of the aged samples is computed across the entire DPI frequency range for a variety of stress time duration. The proposed log-linear accelerated life-stress test (ALT) model is combined with the Weibull unreliability distribution function model to estimate the failure lifetime data against the applied voltage stress at three different failure threshold criterion. At various constant voltage overstress and threshold constraints, the lifetime reliability performance parameters (i.e., time-to-failure, probability of failure, model constants) of the tested device under tests (DUTs) were evaluated based on the measured degradation data. It is demonstrated that, for a limited number of samples under the combined influence of thermal step-stress with voltage overstress conditions, the proposed reliability model predicts with a very acceptable accuracy the lifetime reliability of both UA78L05 and L78L05 tested ICs, developed based on the conducted immunity degradation data. The physics-based modeling approach is utilized to develop the model for the degradation paths based on the observed monotonic degradation of the measured degradation data as well as the conditions of the thermal step-stress ADT. In order to estimate the unknown parameters of the developed degradation model, the maximum likelihood estimation (MLE) method is combined with a genetic optimisation algorithm.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":null,"pages":null},"PeriodicalIF":2.5000,"publicationDate":"2023-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Device and Materials Reliability","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10347530/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
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Abstract

This paper presents an approach to develop degradation and reliability models of analog integrated circuit (IC) voltage regulators based on the long-term evolution of the electromagnetic compatibility (EMC) performance degradation due to the stress time-dependent accelerated degradation test (ADT). The ADT plan is designed and conducted on six samples of both UA78L05 and L78L05 ICs placed inside a climatic chamber combining both the thermal step-stress (i.e., 70-110 °C) and constant electrical overstress (i.e., 9 and 12 V) conditions for a total stress duration of 950 hours. All the selected UA78L05 and L78L05 samples are subjected to the direct power injection (DPI) measurement test under nominal conditions in order to characterize their immunity to electromagnetic interference (EMI). The statistical degradation data (i.e., the average injected power) of the aged samples is computed across the entire DPI frequency range for a variety of stress time duration. The proposed log-linear accelerated life-stress test (ALT) model is combined with the Weibull unreliability distribution function model to estimate the failure lifetime data against the applied voltage stress at three different failure threshold criterion. At various constant voltage overstress and threshold constraints, the lifetime reliability performance parameters (i.e., time-to-failure, probability of failure, model constants) of the tested device under tests (DUTs) were evaluated based on the measured degradation data. It is demonstrated that, for a limited number of samples under the combined influence of thermal step-stress with voltage overstress conditions, the proposed reliability model predicts with a very acceptable accuracy the lifetime reliability of both UA78L05 and L78L05 tested ICs, developed based on the conducted immunity degradation data. The physics-based modeling approach is utilized to develop the model for the degradation paths based on the observed monotonic degradation of the measured degradation data as well as the conditions of the thermal step-stress ADT. In order to estimate the unknown parameters of the developed degradation model, the maximum likelihood estimation (MLE) method is combined with a genetic optimisation algorithm.
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基于 ADT 的电压调节器电磁鲁棒性的退化和可靠性建模:方法与案例研究
本文介绍了一种基于应力时间相关加速降解试验(ADT)引起的电磁兼容性(EMC)性能降解的长期演变来开发模拟集成电路(IC)稳压器降解和可靠性模型的方法。ADT 计划是针对 UA78L05 和 L78L05 集成电路的六个样品设计和实施的,这些样品被放置在一个气候箱内,该气候箱结合了热阶跃应力(即 70-110 °C)和恒定电气过应力(即 9 和 12 V)条件,总应力持续时间为 950 小时。所有选定的 UA78L05 和 L78L05 样品都在额定条件下进行了直接功率注入(DPI)测量测试,以鉴定其抗电磁干扰(EMI)能力。计算了老化样品在各种应力时间持续时间内整个 DPI 频率范围内的统计劣化数据(即平均注入功率)。提出的对数线性加速寿命应力测试 (ALT) 模型与 Weibull 不可靠度分布函数模型相结合,在三种不同的失效阈值标准下,根据施加的电压应力估算失效寿命数据。在不同的恒定电压过应力和阈值约束条件下,根据测得的退化数据评估了被测器件(DUT)的寿命可靠性能参数(即失效时间、失效概率、模型常数)。结果表明,在热阶跃应力和电压过应力条件的共同影响下,对于数量有限的样品,根据传导抗扰度退化数据建立的可靠性模型可以非常准确地预测 UA78L05 和 L78L05 测试集成电路的寿命可靠性。利用基于物理的建模方法,根据测量降解数据中观察到的单调降解以及热阶跃应力 ADT 条件建立降解路径模型。为了估计所开发降解模型的未知参数,最大似然估计 (MLE) 方法与遗传优化算法相结合。
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来源期刊
IEEE Transactions on Device and Materials Reliability
IEEE Transactions on Device and Materials Reliability 工程技术-工程:电子与电气
CiteScore
4.80
自引率
5.00%
发文量
71
审稿时长
6-12 weeks
期刊介绍: The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.
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