Xuanxu Chen , Yuejun Zhang , Guangpeng Ai , Lixun Wang , Huihong Zhang , Xiangyu Li , Pengjun Wang
{"title":"Distance optimization KNN and EMD based lightweight hardware IP core design for EEG epilepsy detection","authors":"Xuanxu Chen , Yuejun Zhang , Guangpeng Ai , Lixun Wang , Huihong Zhang , Xiangyu Li , Pengjun Wang","doi":"10.1016/j.mejo.2024.106335","DOIUrl":null,"url":null,"abstract":"<div><p>Long-term and effective detection of epileptic seizures is a crucial aspect of epilepsy monitoring and treatment. Addressing the resource overhead issue of wearable epilepsy detection devices, this paper proposes a lightweight hardware implementation scheme for epilepsy detection based on a reusable architecture empirical mode decomposition (EMD) and K-Nearest Neighbors (KNN). Firstly, EMD is used to extract epileptic features from electroencephalogram (EEG), optimized through a reusable architecture design and sawtooth transform to reduce hardware resource usage. Subsequently, a KNN classifier with similarity judgment mechanism is designed to improve the recognition efficiency. Implemented on TSMC 65 nm process, the circuit area is 1.91 mm<sup>2</sup>, operates at 1 V and 20 MHz, with a power consumption of 4.034 mW. Evaluation on the Bonn EEG dataset yielded a classification accuracy of 96 %, sensitivity of 98 %, and a single detection delay of 1.51 ms. The hardware design offers a simple structure, high accuracy, and low resource consumption, making it suitable for wearable epilepsy detection devices.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2024-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239124000390","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Long-term and effective detection of epileptic seizures is a crucial aspect of epilepsy monitoring and treatment. Addressing the resource overhead issue of wearable epilepsy detection devices, this paper proposes a lightweight hardware implementation scheme for epilepsy detection based on a reusable architecture empirical mode decomposition (EMD) and K-Nearest Neighbors (KNN). Firstly, EMD is used to extract epileptic features from electroencephalogram (EEG), optimized through a reusable architecture design and sawtooth transform to reduce hardware resource usage. Subsequently, a KNN classifier with similarity judgment mechanism is designed to improve the recognition efficiency. Implemented on TSMC 65 nm process, the circuit area is 1.91 mm2, operates at 1 V and 20 MHz, with a power consumption of 4.034 mW. Evaluation on the Bonn EEG dataset yielded a classification accuracy of 96 %, sensitivity of 98 %, and a single detection delay of 1.51 ms. The hardware design offers a simple structure, high accuracy, and low resource consumption, making it suitable for wearable epilepsy detection devices.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc.
Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.