N-DIBL optimization of NC-GAAFET NW for low power fast switching applications

Abstract

Gate-all-around field effect transistors (GAAFETs), exhibit improved SCEs, are proposed to replace conventional FinFET in scaled nanodevices owing to excellent gate control. The voltage scaling concept is embodied in negative capacitance (NC) which provides same on current at reduced voltage. The proposed NC-GAAFET yields 5.31 times larger I_ON and I_OFF is significantly reduced by ⁓10⁵ orders, which is due NC effect, compared to baseline NW. SS_avg for the NC-GAAFET is 33mV/dec which surpasses Boltzmann tyranny and manifests steep subthreshold behavior. Effect of FE thickness (t_fe) variations on DIBL has been explored and found to be negative, which improves SCEs. The negative-DIBL for device has been found to be −20 mV/V at t_fe = 6 nm. Furthermore, a CMOS inverter circuit employing the NC-GAAFET has been presented that provides an average propagation delay of 174 fS which is 47 % lesser as compared to that of baseline device. The NC-GAAFET NW findings fulfill the quest of low power fast switching device for digital applications.