A V-band injection locking tripler with 26.8% locking range and 7.3-dBm output power in 65 nm CMOS

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Microelectronics Journal Pub Date : 2024-09-30 DOI:10.1016/j.mejo.2024.106426

Yue Liang , Qin Chen , Jing Feng , Lin Lu , Tao Zhang , Xiangning Fan , Lianming Li

{"title":"A V-band injection locking tripler with 26.8% locking range and 7.3-dBm output power in 65 nm CMOS","authors":"Yue Liang , Qin Chen , Jing Feng , Lin Lu , Tao Zhang , Xiangning Fan , Lianming Li","doi":"10.1016/j.mejo.2024.106426","DOIUrl":null,"url":null,"abstract":"<div><div>With a 65-nm CMOS process, a V-band wideband injection locking (IL) frequency tripler is proposed by cascading a multiplier and a driver amplifier stage. Concerning high output power and efficiency performance over a wideband locking range (LR), two transformer-based IL topologies are analyzed in the multiplier and driver stages, in which the cross-coupled pair is connected at the input and output ports of the transformer, respectively. Moreover, the active device is carefully designed in terms of the operating point of the harmonic generator and device sizing in the driver amplifier stage. With measurements, the proposed tripler achieves a maximum measured output power of 7.3 dBm with 22.4% output-to-DC power efficiency and 26.8% LR from 50.4 to 66 GHz. Including the output driver amplifier, the IL tripler consumes 24 mW DC power. The measured fundamental and 2nd-harmonic rejection ratios (HRR) are both better than 30 dBc, while the measured phase noise (PN) degradation is in close agreement with the theoretical value.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2024-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239124001309","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

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Abstract

With a 65-nm CMOS process, a V-band wideband injection locking (IL) frequency tripler is proposed by cascading a multiplier and a driver amplifier stage. Concerning high output power and efficiency performance over a wideband locking range (LR), two transformer-based IL topologies are analyzed in the multiplier and driver stages, in which the cross-coupled pair is connected at the input and output ports of the transformer, respectively. Moreover, the active device is carefully designed in terms of the operating point of the harmonic generator and device sizing in the driver amplifier stage. With measurements, the proposed tripler achieves a maximum measured output power of 7.3 dBm with 22.4% output-to-DC power efficiency and 26.8% LR from 50.4 to 66 GHz. Including the output driver amplifier, the IL tripler consumes 24 mW DC power. The measured fundamental and 2nd-harmonic rejection ratios (HRR) are both better than 30 dBc, while the measured phase noise (PN) degradation is in close agreement with the theoretical value.

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采用 65 纳米 CMOS 的 V 波段注入锁定三分频器，锁定范围达 26.8%，输出功率为 7.3 dBm

利用 65 纳米 CMOS 工艺，通过级联乘法器和驱动放大器级，提出了一种 V 波段宽带注入锁定（IL）三倍频器。为了在宽带锁定范围（LR）内实现高输出功率和高效性能，在乘法器和驱动器级中分析了两种基于变压器的 IL 拓扑，其中交叉耦合对分别连接在变压器的输入和输出端口。此外，还根据谐波发生器的工作点和驱动放大器级的器件尺寸，对有源器件进行了精心设计。通过测量，拟议的三倍频器在 50.4 至 66 GHz 范围内实现了 7.3 dBm 的最大测量输出功率，输出到直流电源的功率效率为 22.4%，LR 为 26.8%。包括输出驱动放大器在内，IL 三倍频器的直流功耗为 24 mW。测量的基波和二次谐波抑制比 (HRR) 均优于 30 dBc，而测量的相位噪声 (PN) 衰减与理论值非常接近。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.

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