Preventing short violations in clock routing with an SVM classifier before powerplanning and placement

Abstract

This paper introduces a comprehensive predictive framework utilizing a Support Vector Machine (SVM) classifier to prevent short violations in clock routing prior to powerplanning and placement. Leveraging complex patterns in power mesh configurations and relevant features, the framework enables the SVM classifier to achieve at least 82.6% F1-score and 82.0% accuracy across five cross-tests with open-source benchmarks. The SVM classifier also demonstrates its capability to predict whether short violations will occur in clock routing, effectively selecting nearly or more than 1/2 of the original 150 instances in each of the five benchmarks, resulting in relatively fewer Design Rule Check (DRC) violations after all routing. Moreover, across five cross-tests with 150 instances per benchmark, the classifier filters out at least 1/3 of the configurations vulnerable to clock routing short violations, thereby saving the operational time otherwise required for these configurations.