{"title":"An improved 4H-SiC trench MOS barrier Schottky diode with current spreading layer and low resistance layer","authors":"Hai-tao Ge , Wang-zi-xuan Zhen , Cheng-hao Yu , Masayuki yamamoto , Wen-sheng Zhao , Hao-min Guo , Xiao-dong Wu","doi":"10.1016/j.mejo.2024.106451","DOIUrl":null,"url":null,"abstract":"<div><div>This paper investigates an improved trench MOS barrier Schottky (TMBS) structure with extra double epitaxial layers (DE-TMBS) based on the conventional TMBS (C-TMBS) featuring a high-doped N-type current spreading layer (CSL) and a high-doped low resistance layer (LRL). Compared to the C-TMBS, the CSL in the improved structure is grown on the N-type drift region, and the LRL is extended on the CSL. According to the numerical simulations and analytical models, the specific on-resistance (<em>R</em><sub>on,sp</sub>) of DE-TMBS can be significantly reduced compared to the conventional one. This is primarily due to the high doping concentration in CSL, which effectively lowers both the JFET resistance and spreading resistance. Additionally, the increased doping concentration in LRL reduces the channel resistance and JFET resistance. Moreover, the doping concentration and thickness of CSL and LRL are optimized to maximize the figure of merit (FOM), that <em>R</em><sub>on,sp</sub> is reduced by 40.9 % and the FOM (<em>BV</em><sup><em>2</em></sup>/<em>R</em><sub>on,sp</sub>) is improved by 67.9 % compared to the C-TMBS structure.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239124001553","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This paper investigates an improved trench MOS barrier Schottky (TMBS) structure with extra double epitaxial layers (DE-TMBS) based on the conventional TMBS (C-TMBS) featuring a high-doped N-type current spreading layer (CSL) and a high-doped low resistance layer (LRL). Compared to the C-TMBS, the CSL in the improved structure is grown on the N-type drift region, and the LRL is extended on the CSL. According to the numerical simulations and analytical models, the specific on-resistance (Ron,sp) of DE-TMBS can be significantly reduced compared to the conventional one. This is primarily due to the high doping concentration in CSL, which effectively lowers both the JFET resistance and spreading resistance. Additionally, the increased doping concentration in LRL reduces the channel resistance and JFET resistance. Moreover, the doping concentration and thickness of CSL and LRL are optimized to maximize the figure of merit (FOM), that Ron,sp is reduced by 40.9 % and the FOM (BV2/Ron,sp) is improved by 67.9 % compared to the C-TMBS structure.
期刊介绍：
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc.
Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.
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