ANN-Driven Modeling of Gate-All-Around Transistors Incorporating Complete Current Profiles

IF 2.1 4区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Nanotechnology Pub Date : 2025-02-14 DOI:10.1109/TNANO.2025.3542165
Anant Singhal;Harshit Agarwal
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Abstract

In this article, we present an Artificial Neural Network (ANN)-based compact model that accurately captures the complete current characteristics of gate-all-around transistors, including drain, gate, and substrate currents. Unlike previous models, our approach simplifies the modeling of substrate current by defining a simple conversion function and by utilizing simpler loss functions that account for physical effects such as impact ionization. This accurate representation of substrate current is critical for addressing hot-carrier-induced reliability concerns. The proposed model is extensively validated with calibrated Technology Computer-Aided Design (TCAD) simulations as well as with experimental data from multiple technologies. Additionally, it demonstrates smooth higher-order derivatives in symmetry tests, ensuring its suitability for RF applications.
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来源期刊
IEEE Transactions on Nanotechnology
IEEE Transactions on Nanotechnology 工程技术-材料科学:综合
CiteScore
4.80
自引率
8.30%
发文量
74
审稿时长
8.3 months
期刊介绍: The IEEE Transactions on Nanotechnology is devoted to the publication of manuscripts of archival value in the general area of nanotechnology, which is rapidly emerging as one of the fastest growing and most promising new technological developments for the next generation and beyond.
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