On-chip resistors are susceptible to temperature variations, affecting the performance of linear voltage-to-current (VI) conversion and vice versa. This paper introduces an approach to implement resistive networks that are highly immune to temperature variations across a wide range by combining complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) resistors existing in standard CMOS technology. The proposed resistive networks, aiming for linear VI conversion in voltage and current references (VCRs), yield ultra-low temperature coefficient (TC). Optimization is carried out using a multi-objective heuristic algorithm to find the optimal placement, TC and sizes of the elements within the final configuration. Post-layout simulation results in a standard 0.18-μm CMOS process demonstrate the possibility of implementing sub-3 ppm/°C resistors across −40 ~ 120°C temperature range, improving the prior art by more than 5×. A modern VCR configuration is implemented based on the proposed methodology, and simulation results verify the effectiveness of the modified approach in improving the accuracy of VI conversion.