Using partial reconfigurability to aid debugging of FPGA designs

2011 VII Southern Conference on Programmable Logic (SPL) Pub Date : 2011-04-13 DOI:10.1109/SPL.2011.5782651

A. Ehliar, J. Siverskog

引用次数: 1

Abstract

This paper discusses the use of partial reconfigurability in Xilinx FPGA designs in order to aid debugging. A debugging framework is proposed where the use of partial reconfigurability can allow for added flexibility by allowing a debugger to decide at run time what debugging module to use. This paper also presents an open source debugging tool which allows a user to read-out the contents of memory blocks in Xilinx designs without needing to use any JTAG adapter. This allows a user to debug an FPGA in situations which would otherwise be difficult, i.e. in the field.

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利用部分可重构性帮助FPGA设计调试

本文讨论了部分可重构性在Xilinx FPGA设计中的应用，以帮助调试。本文提出了一个调试框架，其中部分可重构性的使用允许调试器在运行时决定使用哪个调试模块，从而增加了灵活性。本文还介绍了一个开源调试工具，它允许用户在不使用任何JTAG适配器的情况下读取Xilinx设计中的内存块的内容。这允许用户在困难的情况下调试FPGA，即在现场。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2011 VII Southern Conference on Programmable Logic (SPL)

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