Experiences applying framework-based functional verification to a design for programmable logic

2011 VII Southern Conference on Programmable Logic (SPL) Pub Date : 2011-04-13 DOI:10.1109/SPL.2011.5782634

O. Goni, M. Vazquez, E. Todorovich, G. Sutter

引用次数: 4

Abstract

This paper presents experiences in applying modern functional verification to a configurable decimal floating point Adder / Subtractor core targeted to programmable logic. Despite its huge input space, a number of hard-to-verify corner cases are identified. Two different verification frameworks were applied in order to develop testbenches: OVM and Truss. These tesbenches were built to be independent of the ALU operand representation and IEEE754-2008 specific modules were also implemented. Verification results, the experience itself, and a comparative study of the alternatives was made and summarized for designers and verification engineers.

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有将基于框架的功能验证应用于可编程逻辑设计的经验

本文介绍了将现代功能验证应用于面向可编程逻辑的可配置十进制浮点加/减核的经验。尽管它的输入空间很大，但仍发现了许多难以验证的极端情况。为了开发测试平台，我们应用了两种不同的验证框架:OVM和Truss。这些测试台的构建与ALU操作数表示无关，并且还实现了IEEE754-2008特定模块。对验证结果、经验本身以及备选方案的比较研究进行了总结，供设计人员和验证工程师参考。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2011 VII Southern Conference on Programmable Logic (SPL)

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Using partial reconfigurability to aid debugging of FPGA designs Architecture driven memory allocation for FPGA based real-time video processing systems Soft error in FPGA-implemented asynchronous circuits Experiences applying framework-based functional verification to a design for programmable logic A FPGA IEEE-754-2008 decimal64 Floating-Point adder/subtractor