Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782633
F. Ferrucci, C. Verrastro, G. E. Ríos, D. Estryk
In this work an FPGA-based emulator of a pulse-mode neutron detector system is presented. The equipment emulates the digital output of a discriminator circuit and permits the generation of pulse trains ranging from 0.5 pulse/s to 1 Mpulse/s. The emulation is based on a synchronous version of a Poisson process generator using Bernoulli trials. The emulator is controlled via a serial connection to a computer and both the pulse-width and the mean pulse-rate can be dynamically updated; thus, making possible the emulation of a detector evolution when a nuclear reactor is in its start-up/shutting-down phase. To also consider the dead-time effects present in pulse-mode detector systems, the equipment implements the paralyzable and nonparalyzable dead-time models. The emulator also incorporates a data-logger module to record interarrival-time values of the generated pulse train. This last feature can be used to calibrate a rate-meter equipment and to verify the statistics of the emulator's output signal.
{"title":"FPGA-based random pulse generator for emulation of a neutron detector system in a nuclear reactor","authors":"F. Ferrucci, C. Verrastro, G. E. Ríos, D. Estryk","doi":"10.1109/SPL.2011.5782633","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782633","url":null,"abstract":"In this work an FPGA-based emulator of a pulse-mode neutron detector system is presented. The equipment emulates the digital output of a discriminator circuit and permits the generation of pulse trains ranging from 0.5 pulse/s to 1 Mpulse/s. The emulation is based on a synchronous version of a Poisson process generator using Bernoulli trials. The emulator is controlled via a serial connection to a computer and both the pulse-width and the mean pulse-rate can be dynamically updated; thus, making possible the emulation of a detector evolution when a nuclear reactor is in its start-up/shutting-down phase. To also consider the dead-time effects present in pulse-mode detector systems, the equipment implements the paralyzable and nonparalyzable dead-time models. The emulator also incorporates a data-logger module to record interarrival-time values of the generated pulse train. This last feature can be used to calibrate a rate-meter equipment and to verify the statistics of the emulator's output signal.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81282356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782623
Maciej Kurek, Ioannis Ilkos, W. Luk
This paper describes a security-aware cache targeting field-programmable gate array (FPGA) technology. Our design is based on an architecture with a remapping table, which provides resilience against side-channel timing attacks. We show how this cache design can be optimised for FPGA resources by an index decoder with content addressable memory structure, which can be customized to meet various requirements. We show, for the first time, how our security-aware cache can be included in the Leon 3 processor, and its performance and resource usage are evaluated.
{"title":"Customizable security-aware cache for FPGA-based soft processors","authors":"Maciej Kurek, Ioannis Ilkos, W. Luk","doi":"10.1109/SPL.2011.5782623","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782623","url":null,"abstract":"This paper describes a security-aware cache targeting field-programmable gate array (FPGA) technology. Our design is based on an architecture with a remapping table, which provides resilience against side-channel timing attacks. We show how this cache design can be optimised for FPGA resources by an index decoder with content addressable memory structure, which can be customized to meet various requirements. We show, for the first time, how our security-aware cache can be included in the Leon 3 processor, and its performance and resource usage are evaluated.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90308068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782657
Carlos Minchola, M. Vazquez, G. Sutter
This paper describes the FPGA implementation of a Decimal Floating Point (DFP) adder/subtractor. The design performs addition and subtraction on 64-bit operands that use the IEEE 754-2008 decimal encoding of DFP numbers and is based on a fully pipelined circuit. The design presents a novel hardware for pre-signal generation stage and an enhanced version of previously published leading zero stage. The design can operate at a frequency of 200 MHZ on a Virtex-5 with a latency of 8 cycles. The presented DFP adder/subtractor supports operations on the decimal64 format and it is easily extendable for the decimal128 format. To our knowledge, this is the first hardware FPGA design for adding and subtracting IEEE 754-2008 using decimal64 encoding.
{"title":"A FPGA IEEE-754-2008 decimal64 Floating-Point adder/subtractor","authors":"Carlos Minchola, M. Vazquez, G. Sutter","doi":"10.1109/SPL.2011.5782657","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782657","url":null,"abstract":"This paper describes the FPGA implementation of a Decimal Floating Point (DFP) adder/subtractor. The design performs addition and subtraction on 64-bit operands that use the IEEE 754-2008 decimal encoding of DFP numbers and is based on a fully pipelined circuit. The design presents a novel hardware for pre-signal generation stage and an enhanced version of previously published leading zero stage. The design can operate at a frequency of 200 MHZ on a Virtex-5 with a latency of 8 cycles. The presented DFP adder/subtractor supports operations on the decimal64 format and it is easily extendable for the decimal128 format. To our knowledge, this is the first hardware FPGA design for adding and subtracting IEEE 754-2008 using decimal64 encoding.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74136040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782616
E. Marchi, M. Cervetto, Marcelo L. Tenorio
The ISDB-T standard for digital broadcasting incorporates an extensive signal processing scheme in order to achieve reliable data integrity at the remote receiver. Particularly, the time interleaving stage requires a significant memory depth. Common implementations are often based in single-address access memories, which simplifies the algorithm logic but does not provide a cost-effective solution. This paper presents a DDR3 memory based FPGA implementation of the ISDB-T time interleaving stage. Widely available on the market for a broad type of applications, this kind of memory allows high data throughput and represents a low cost alternative. However, data must comply with a special structure and signalling since the memory access is burst-oriented. Consequently, the complexity is increased. The proposed design is both area-efficient and highly reconfigurable.
{"title":"A DDR3 memory based time interleaving FPGA implementation for ISDB-T standard","authors":"E. Marchi, M. Cervetto, Marcelo L. Tenorio","doi":"10.1109/SPL.2011.5782616","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782616","url":null,"abstract":"The ISDB-T standard for digital broadcasting incorporates an extensive signal processing scheme in order to achieve reliable data integrity at the remote receiver. Particularly, the time interleaving stage requires a significant memory depth. Common implementations are often based in single-address access memories, which simplifies the algorithm logic but does not provide a cost-effective solution. This paper presents a DDR3 memory based FPGA implementation of the ISDB-T time interleaving stage. Widely available on the market for a broad type of applications, this kind of memory allows high data throughput and represents a low cost alternative. However, data must comply with a special structure and signalling since the memory access is burst-oriented. Consequently, the complexity is increased. The proposed design is both area-efficient and highly reconfigurable.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77763836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782632
Marcelo J. Segura, C. Sisterna, Martin Guzzo, Gustavo Ensinck, Carlos Gil
In impulse-based UWB systems, positional accuracy is inversely proportional to the signal bandwidth. In this work, a number of anchor nodes are located at fixed positions in an indoor environment transmitting synchronized 2.5ns pulses with Differential Binary Phase Shift Keying (DBPSK) modulation. An UWB receiver mounted on a mobile robot utilizes Time Difference of Arrival (TDOA) between pairs of synchronized transmitting anchor nodes for localization. Self-localization implies that position estimation algorithms run locally on the mobile robot. A prototype non-coherent UWB receiver using off-the-shelf components is implemented where signal acquisition runs on a Field Programmable Gate Array (FPGA). Measurement results indicate sub-20cm positional accuracy with Line Of Sight (LOS) and Non-Line of Sight (NLOS) conditions relative to fixed anchor nodes in a typical indoor environment.
{"title":"Ultra wideband digital receiver implemented on FPGA for mobile robot indoor self-localization","authors":"Marcelo J. Segura, C. Sisterna, Martin Guzzo, Gustavo Ensinck, Carlos Gil","doi":"10.1109/SPL.2011.5782632","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782632","url":null,"abstract":"In impulse-based UWB systems, positional accuracy is inversely proportional to the signal bandwidth. In this work, a number of anchor nodes are located at fixed positions in an indoor environment transmitting synchronized 2.5ns pulses with Differential Binary Phase Shift Keying (DBPSK) modulation. An UWB receiver mounted on a mobile robot utilizes Time Difference of Arrival (TDOA) between pairs of synchronized transmitting anchor nodes for localization. Self-localization implies that position estimation algorithms run locally on the mobile robot. A prototype non-coherent UWB receiver using off-the-shelf components is implemented where signal acquisition runs on a Field Programmable Gate Array (FPGA). Measurement results indicate sub-20cm positional accuracy with Line Of Sight (LOS) and Non-Line of Sight (NLOS) conditions relative to fixed anchor nodes in a typical indoor environment.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81401128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782629
Thomas P. Perry, R. Walke, K. Benkrid
In this paper, we examine the problem of abstracting the design process for heterogeneous CPU/FPGA systems from the perspective of a group of engineers designing telecommunications systems, and propose a design flow that addresses the constraints imposed in an industrial context whilst striving for maximal compatibility with existing tools and research projects. We thus present a modular and extensible flow based around the IP-XACT standard, which is gaining support in industry, and link this to a front-end built on the semantics of dataflow process networks and a template-based code generation back-end.
{"title":"An extensible code generation framework for heterogeneous architectures based on IP-XACT","authors":"Thomas P. Perry, R. Walke, K. Benkrid","doi":"10.1109/SPL.2011.5782629","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782629","url":null,"abstract":"In this paper, we examine the problem of abstracting the design process for heterogeneous CPU/FPGA systems from the perspective of a group of engineers designing telecommunications systems, and propose a design flow that addresses the constraints imposed in an industrial context whilst striving for maximal compatibility with existing tools and research projects. We thus present a modular and extensible flow based around the IP-XACT standard, which is gaining support in industry, and link this to a front-end built on the semantics of dataflow process networks and a template-based code generation back-end.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82870235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782660
C. Valderrama, L. Jojczyk, P. DaCunha Possa, J. D. Dondo Gazzano
The growing demands on multimedia applications and high-speed high-quality telecommunication systems with real-time constrains oriented to portable, low power consumption, devices, have being driven technologies development, methodologies and design flows of embedded systems during the last years. Through the analysis of design methodologies and strategies facing multi-core, reconfigurability and power consumption challenges, this educational survey will follow that evolution approaching ASIC and FPGA architectures on the embedded systems arena.
{"title":"FPGA and ASIC convergence","authors":"C. Valderrama, L. Jojczyk, P. DaCunha Possa, J. D. Dondo Gazzano","doi":"10.1109/SPL.2011.5782660","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782660","url":null,"abstract":"The growing demands on multimedia applications and high-speed high-quality telecommunication systems with real-time constrains oriented to portable, low power consumption, devices, have being driven technologies development, methodologies and design flows of embedded systems during the last years. Through the analysis of design methodologies and strategies facing multi-core, reconfigurability and power consumption challenges, this educational survey will follow that evolution approaching ASIC and FPGA architectures on the embedded systems arena.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88685088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782625
A. Morillo, A. Astarloa, Jesús Lázaro, U. Bidarte, J. Jiménez
The need of critical applications has derived in the development of several safety techniques that aim to guarantee system operability. The vast majority of these systems own a microprocessor to control its functionality. Thus, system reliability largely depends on the proper function of the microprocessor. In the special case of SRAM FPGAs, Triple Modular Redundancy (TMR) combined with Dynamic Partial Reconfiguration (DPR) allows the development of coarse grain modularity architectures where the redundant module is a soft-core microprocessor or a more complex logical unit based in a processor. However, its main lack is a suitable synchronization method for the faulty module once it is reconfigured. This paper shows the trends on synchronization methods for systems that make use of TMR and DPR and proposes a new synchronization method based on a non blocking scheme.
{"title":"Known-blocking. Synchronization method for reliable processor using TMR & DPR in SRAM FPGAs","authors":"A. Morillo, A. Astarloa, Jesús Lázaro, U. Bidarte, J. Jiménez","doi":"10.1109/SPL.2011.5782625","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782625","url":null,"abstract":"The need of critical applications has derived in the development of several safety techniques that aim to guarantee system operability. The vast majority of these systems own a microprocessor to control its functionality. Thus, system reliability largely depends on the proper function of the microprocessor. In the special case of SRAM FPGAs, Triple Modular Redundancy (TMR) combined with Dynamic Partial Reconfiguration (DPR) allows the development of coarse grain modularity architectures where the redundant module is a soft-core microprocessor or a more complex logical unit based in a processor. However, its main lack is a suitable synchronization method for the faulty module once it is reconfigured. This paper shows the trends on synchronization methods for systems that make use of TMR and DPR and proposes a new synchronization method based on a non blocking scheme.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80043152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782622
J. Finochietto, S. Paz, C. Zerbini
As communication networks move towards 40/100G transmission capacities, wire-speed packet processing is becoming much critical to implement. Most commercial solutions for the high-speed telecom market are based on either ASIC designs and/or network processors (NPs), while enterprise solutions can eventually make use of general purpose processors (GPPs) to deal with much slower processing requirements. As Field-programmable gate array (FPGA) technology continues to evolve, its use for packet processing tasks in network devices is expected to grow. Meanwhile, per-flow processing techniques that scale better than per-packet ones are becoming more widespread in network design. Packet flow processing aims at grouping packets that require similar processing tasks in order to perform them efficiently. This paper proposes the definition of hardware primitives that can be assembled and reused to build packet flow processing architectures. These primitives are described and discussed as well as their interconnection strategy. To illustrate the concept, a case study of an implementation of a packet switch architecture is finally presented.
{"title":"Hardware primitives for packet flow processing architectures","authors":"J. Finochietto, S. Paz, C. Zerbini","doi":"10.1109/SPL.2011.5782622","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782622","url":null,"abstract":"As communication networks move towards 40/100G transmission capacities, wire-speed packet processing is becoming much critical to implement. Most commercial solutions for the high-speed telecom market are based on either ASIC designs and/or network processors (NPs), while enterprise solutions can eventually make use of general purpose processors (GPPs) to deal with much slower processing requirements. As Field-programmable gate array (FPGA) technology continues to evolve, its use for packet processing tasks in network devices is expected to grow. Meanwhile, per-flow processing techniques that scale better than per-packet ones are becoming more widespread in network design. Packet flow processing aims at grouping packets that require similar processing tasks in order to perform them efficiently. This paper proposes the definition of hardware primitives that can be assembled and reused to build packet flow processing architectures. These primitives are described and discussed as well as their interconnection strategy. To illustrate the concept, a case study of an implementation of a packet switch architecture is finally presented.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79976693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782646
L. De Micco, H. Larrondo
The dual deterministic-stochastic behavior of chaotic systems (CS) makes them extremely interesting in electronic engineering as CS may replace noise sources in different applications. Consequently it is convenient to have hardware implementations for both, analog and digital versions. Discrete components, Micro Controllers, Digital Signal Processors (DSP) and Field Programmable Gate Arrays (FPGAs) are possible choices.
{"title":"FPGA implementation of a chaotic oscillator using RK4 method","authors":"L. De Micco, H. Larrondo","doi":"10.1109/SPL.2011.5782646","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782646","url":null,"abstract":"The dual deterministic-stochastic behavior of chaotic systems (CS) makes them extremely interesting in electronic engineering as CS may replace noise sources in different applications. Consequently it is convenient to have hardware implementations for both, analog and digital versions. Discrete components, Micro Controllers, Digital Signal Processors (DSP) and Field Programmable Gate Arrays (FPGAs) are possible choices.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88875752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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