A Comprehensive Study of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Layer Effects on Negative Capacitance FETs for Sub-5 nm Node
Y. Tang, C. Su, Y.-S. Wang, K. Kao, T.-L. Wu, P. Sung, F. Hou, C. Wang, M. Yeh, Y. Lee, W. Wu, G. Huang, J. Shieh, W. Yeh, Y. Wang
{"title":"A Comprehensive Study of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Layer Effects on Negative Capacitance FETs for Sub-5 nm Node","authors":"Y. Tang, C. Su, Y.-S. Wang, K. Kao, T.-L. Wu, P. Sung, F. Hou, C. Wang, M. Yeh, Y. Lee, W. Wu, G. Huang, J. Shieh, W. Yeh, Y. Wang","doi":"10.1109/VLSIT.2018.8510696","DOIUrl":null,"url":null,"abstract":"The impact of a realistic representation of gate-oxide granularity on negative-capacitance (NC) FETs at sub-5nm node is studied by a newly developed thermodynamic energy model based on the first principle calculation (FPC). For the first time, the calculation fully couples the Landau-Khalatnikov (L-K) equation with grain-size effect equation in NC-FETs. It explains the experimental results in phase transition and reveals excellent immunity against depolarization in ferroelectric (FE) layer owing to dopant concentration and stress in thin films. A sub-5nm node (LG=10nm) NC-FET with thin FE layer (TFE~2nm) is integrated to achieve low subthreshold slope (SS) of 52mV/dec via a 1.9GPa-tensor stressed interfacial layer (IL) and 12% Zr-doped HfO2.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"16 1","pages":"45-46"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2018.8510696","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
The impact of a realistic representation of gate-oxide granularity on negative-capacitance (NC) FETs at sub-5nm node is studied by a newly developed thermodynamic energy model based on the first principle calculation (FPC). For the first time, the calculation fully couples the Landau-Khalatnikov (L-K) equation with grain-size effect equation in NC-FETs. It explains the experimental results in phase transition and reveals excellent immunity against depolarization in ferroelectric (FE) layer owing to dopant concentration and stress in thin films. A sub-5nm node (LG=10nm) NC-FET with thin FE layer (TFE~2nm) is integrated to achieve low subthreshold slope (SS) of 52mV/dec via a 1.9GPa-tensor stressed interfacial layer (IL) and 12% Zr-doped HfO2.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
