Selector Requirements for Tera-Bit Ultra-High-Density 3D Vertical RRAM

Abstract

Selector requirements for tera-bit class, ultra-high-density 3D vertical resistive random access memory (VRRAM) are presented, including practical design considerations such as array efficiency (AE), pillar driver transistors (pillar drivers), and wire/metal plane resistances. We design a novel chip architecture that is different from 3D NAND: (a) separated, square and large wordplane (WP) connected by global wordplane connections (WPC) within a block to minimize influence of leakage currents, (b) compact staircase. An accurate, computationally efficient resistor network is developed to model the parasitic resistances of the architecture. Through the resistor network simulations, selector requirements for 3D VRRAM are examined. To achieve tera-bit class 3D VRRAM with density higher than the most advanced 3D NAND flash (> 4.3 Gb/mm2), selector nonlinearity (NL) ≥ 102 is required.