H. Sagong, K. Choi, J. Kim, T. Jeong, M. Choe, H. Shim, W. Kim, J. Park, S. Shin, S. Pae
{"title":"Modeling of FinFET Self-Heating Effects in multiple FinFET Technology Generations with implication for Transistor and Product Reliability","authors":"H. Sagong, K. Choi, J. Kim, T. Jeong, M. Choe, H. Shim, W. Kim, J. Park, S. Shin, S. Pae","doi":"10.1109/VLSIT.2018.8510657","DOIUrl":null,"url":null,"abstract":"We report the characterization and modeling of FinFET self-heating (FSH) and its reliability impact across multiple FinFET process technology generations. With technology node scaling, taller and narrower Fin shape allows higher performance. However, increased FSH and potential reliability issues must be well understood and mitigated. This paper presents FSH effects across multiple technology nodes and characterization, and modeling efforts used in design will be presented. The results on transistor and product level demonstrate excellent reliability performance beyond 10yrs","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"11 1","pages":"121-122"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2018.8510657","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
We report the characterization and modeling of FinFET self-heating (FSH) and its reliability impact across multiple FinFET process technology generations. With technology node scaling, taller and narrower Fin shape allows higher performance. However, increased FSH and potential reliability issues must be well understood and mitigated. This paper presents FSH effects across multiple technology nodes and characterization, and modeling efforts used in design will be presented. The results on transistor and product level demonstrate excellent reliability performance beyond 10yrs