WLCSP Package and PCB Design for Board Level Reliability

Abstract

WLCSP packaging is wildly use in portable electronic products such as phone, watch, and intelligent bracelet. The advantages of WLCSP package are parasitic inductance minimized, reduced package size, and enhanced thermal conduction characteristics. To enable these benefits regardless of the die's functional complexity, we adopted Cu with ELK (extreme Low-K) material as inter-metal-dielectric native to advanced silicon fabrication technology, and WLCSP packing with large die size, thus fulfilling requirements for high speed & low power consumption. To investigate wafer WLCSP board level reliability performance is essential and critical for successful product launch and preventing field return risk. Test vehicles were used with combinations in PBO2 opening, PCB thickness, and PCB metal gradient, to understand stress on ELK behavior and potential impact on board level reliability. A quick stress test methodology using 75 cycles of -650C~1500C liquid-to-liquid thermal shock (LLTS), showing ~acceleration factor of 1.9 compared with TCB stress, was validated and used for shortening experiment cycle time. A 6x6 mm2 test vehicle was used for different WLCSP package PBO2 opening, PCB thickness and PCB metal design to assess board level reliability impact. LLTS 75cycles result showed larger PBO2 opening will get die edge ELK delamination defects. Higher PCB metal gradient board (more than 50%) & more thick (1mm) also got higher fail rate. For better WLCSP board level reliability structure, smaller WLCSP package PBO2 opening, thinner PCB thickness and uniform PCB metal distribution are recommended.