Hanqing Jiang, Han Zhou, S. Robertson, Zhaoxia Zhou, Liguo Zhao, Changqing Liu
Due to the demand of miniaturization and increasing functionality in power electronics, thermal dissipation becomes a challenging problem for thermal management and reliability. To enable effective heat transfer across the interconnect interfaces, thermal interface materials (TIMs) are required. Electrically insulating TIMs are primarily polymer-based composites which use conductive fillers to enhance thermal conductivity (TC). In this study, the optimal hybrid filler constituents, achieved through mixing spherical and platelet h-BN particles with different ratios, in polymer-based TIM was predicted using finite element (FE) simulations. The underpinning mechanisms of the variation in TC of the TIMs were analyzed from the temperature distribution patterns and micro heat flux paths. Results showed that with the same total volume fraction of h-BN, mixed spherical and platelet h-BN fillers of a certain ratio can further improve the thermal properties of the TIMs compared with those with spherical or platelet h-BN particles alone.
{"title":"Further Enhancement of Thermal Conductivity through Optimal Uses of h-BN Fillers in Polymer-Based Thermal Interface Material for Power Electronics","authors":"Hanqing Jiang, Han Zhou, S. Robertson, Zhaoxia Zhou, Liguo Zhao, Changqing Liu","doi":"10.1109/ECTC.2019.00241","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00241","url":null,"abstract":"Due to the demand of miniaturization and increasing functionality in power electronics, thermal dissipation becomes a challenging problem for thermal management and reliability. To enable effective heat transfer across the interconnect interfaces, thermal interface materials (TIMs) are required. Electrically insulating TIMs are primarily polymer-based composites which use conductive fillers to enhance thermal conductivity (TC). In this study, the optimal hybrid filler constituents, achieved through mixing spherical and platelet h-BN particles with different ratios, in polymer-based TIM was predicted using finite element (FE) simulations. The underpinning mechanisms of the variation in TC of the TIMs were analyzed from the temperature distribution patterns and micro heat flux paths. Results showed that with the same total volume fraction of h-BN, mixed spherical and platelet h-BN fillers of a certain ratio can further improve the thermal properties of the TIMs compared with those with spherical or platelet h-BN particles alone.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"594 1","pages":"1569-1574"},"PeriodicalIF":0.0,"publicationDate":"2019-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85340694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a novel design of a bandwidth enhanced dual-band impedance matching network utilizing the principle of wave slowing. Coupled-line sections have been used in their all-pass configuration to incorporate the same. The proposed design is generalized for real as well as complex loads with simple closed form design equations. The design is compact and robust and solves the hurdle of bandwidth crunch at GSM and near-GSM frequencies. To validate the proposed concept, prototypes have been fabricated on RO5880, which demonstrate wide band performance for real loads at 900MHz and 2.4GHz.
{"title":"A Novel Design of a Bandwidth Enhanced Dual-Band Impedance Matching Network with Coupled Line Wave Slowing","authors":"D. Banerjee, A. Saxena, M. Hashmi","doi":"10.1109/ECTC.2019.00271","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00271","url":null,"abstract":"This paper presents a novel design of a bandwidth enhanced dual-band impedance matching network utilizing the principle of wave slowing. Coupled-line sections have been used in their all-pass configuration to incorporate the same. The proposed design is generalized for real as well as complex loads with simple closed form design equations. The design is compact and robust and solves the hurdle of bandwidth crunch at GSM and near-GSM frequencies. To validate the proposed concept, prototypes have been fabricated on RO5880, which demonstrate wide band performance for real loads at 900MHz and 2.4GHz.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"58 1","pages":"1770-1773"},"PeriodicalIF":0.0,"publicationDate":"2019-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87495912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. England, D. Fisher, K. Rivera, B. Guthrie, Ping-Jui Kuo, Chang-Chi Lee, Che-Ming Hsu, Fan-Yu Min, Kuo-Chang Kang, Chen-Yuan Weng
In order to support emerging applications such as machine learning, where large amounts of fast access memory are required, the use of 3D packaging is inevitable. Previous work on 3D packaging with advanced node logic has shown that the technology is ready for implementation. In this paper, GF and ASE have demonstrated a Die-to-Wafer (D2W) process using 50um thickness logic wafers as the base. The 3D package also includes integrated thermal structures for heat removal from the base logic die. The process flow will be reviewed in detail, and challenges that were faced and overcome will be discussed. Reliability performance of the 3D package will also be reported. In addition, extensive thermal modeling was completed to understand the impact of two competing solutions for heat removal, which will also be reviewed in detail.
{"title":"Die-to-Wafer (D2W) Processing and Reliability for 3D Packaging of Advanced Node Logic","authors":"L. England, D. Fisher, K. Rivera, B. Guthrie, Ping-Jui Kuo, Chang-Chi Lee, Che-Ming Hsu, Fan-Yu Min, Kuo-Chang Kang, Chen-Yuan Weng","doi":"10.1109/ECTC.2019.00096","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00096","url":null,"abstract":"In order to support emerging applications such as machine learning, where large amounts of fast access memory are required, the use of 3D packaging is inevitable. Previous work on 3D packaging with advanced node logic has shown that the technology is ready for implementation. In this paper, GF and ASE have demonstrated a Die-to-Wafer (D2W) process using 50um thickness logic wafers as the base. The 3D package also includes integrated thermal structures for heat removal from the base logic die. The process flow will be reviewed in detail, and challenges that were faced and overcome will be discussed. Reliability performance of the 3D package will also be reported. In addition, extensive thermal modeling was completed to understand the impact of two competing solutions for heat removal, which will also be reviewed in detail.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"16 1","pages":"600-606"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74025232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Hsiao, S. W. Ho, S. Lim, L. Wai, S. Chong, Pei Siang Sharon Lim, Yong Han, T. Chai
Today, Package on Package is a major trend of three-dimensional fabrication for processors and high-performance memory applications in portable applications. Package-on-Package has the benefit of a mini packaging size with multi-functionality by stacking two different packs. However, an ordinary Printed circuit board substrate Package on Package has a weak point to meet the now low profile necessary of high-performance in the thin portable application. To overcome this weak point, the package has been introduced to the market by Fan Out Wafer Level, and this structure of the package allows I/O to be within the device surface and expand through the combination of form so that they can be accommodated more FOWLP. Ultra-thin Fan-out PoP was developed using RDL-first process flow. The developed Fan-out PoP has a package size of 15 x 15 mm2 and thickness of 800 µm, and it consists of three embedded chips. The bottom package consists of a 10 x 10 mm2 processor chip assembled to under bump metallization (UBM) of the bottom RDL layers. Vertical wire-bonds are integrated into the bottom package to act as vertical through mold interconnect (TMI) to the top RDL layers. The top package consist of two 7 x 11 mm2 silicon chips assembled laterally on top of the bottom package and connected to the top RDL layer with low-loop wire-bonds. The top chips were encapsulated in epoxy mold compound to form an integrated PoP. RDL-first integration flow was used to fabricate the fan-out package whereby RDL, molding and chips assembly processes were performed on a carrier wafer to overcome warpage associated with conventional Mold-first process. The ultra-thin Fan-out PoP samples pass the reliability include the MST level 3, drop impact test and the Thermal Cycling. It also provides good thermal performance on packaging level and system level applied in mobile device.
今天，包对包是一个主要的趋势，三维制造的处理器和高性能存储器应用在便携式应用。包上包的好处是一个迷你的包装尺寸与多功能堆叠两个不同的包。然而，普通的印刷电路板基板封装在封装上有一个弱点，以满足现在在薄便携式应用中高性能所必需的低轮廓。为了克服这一弱点，该封装已通过扇出晶圆级(Fan Out Wafer Level)推向市场，该封装的这种结构允许I/O位于器件表面内，并通过组合形式进行扩展，从而可以容纳更多的FOWLP。采用RDL-first工艺流程开发了超薄扇形PoP。开发的Fan-out PoP封装尺寸为15 x 15 mm2，厚度为800µm，由三个嵌入式芯片组成。底部封装由一个10 x 10 mm2的处理器芯片组成，组装在底部RDL层的碰撞下金属化(UBM)上。垂直线键集成到底部封装中，作为垂直通过模具互连(TMI)到顶部RDL层。顶部封装由两个7 x 11 mm2的硅芯片组成，横向组装在底部封装的顶部，并通过低环线键连接到顶部RDL层。顶部的芯片被封装在环氧模化合物中，形成一个集成的PoP。RDL-first集成流程用于制造扇形封装，其中RDL，成型和芯片组装过程在载体晶圆上执行，以克服与传统模具-first工艺相关的弯曲。超薄扇出式PoP样品通过了MST 3级、跌落冲击测试和热循环测试。在移动设备的封装级和系统级均具有良好的散热性能。
{"title":"Ultra-Thin FO Package-on-Package for Mobile Application","authors":"H. Hsiao, S. W. Ho, S. Lim, L. Wai, S. Chong, Pei Siang Sharon Lim, Yong Han, T. Chai","doi":"10.1109/ECTC.2019.00011","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00011","url":null,"abstract":"Today, Package on Package is a major trend of three-dimensional fabrication for processors and high-performance memory applications in portable applications. Package-on-Package has the benefit of a mini packaging size with multi-functionality by stacking two different packs. However, an ordinary Printed circuit board substrate Package on Package has a weak point to meet the now low profile necessary of high-performance in the thin portable application. To overcome this weak point, the package has been introduced to the market by Fan Out Wafer Level, and this structure of the package allows I/O to be within the device surface and expand through the combination of form so that they can be accommodated more FOWLP. Ultra-thin Fan-out PoP was developed using RDL-first process flow. The developed Fan-out PoP has a package size of 15 x 15 mm2 and thickness of 800 µm, and it consists of three embedded chips. The bottom package consists of a 10 x 10 mm2 processor chip assembled to under bump metallization (UBM) of the bottom RDL layers. Vertical wire-bonds are integrated into the bottom package to act as vertical through mold interconnect (TMI) to the top RDL layers. The top package consist of two 7 x 11 mm2 silicon chips assembled laterally on top of the bottom package and connected to the top RDL layer with low-loop wire-bonds. The top chips were encapsulated in epoxy mold compound to form an integrated PoP. RDL-first integration flow was used to fabricate the fan-out package whereby RDL, molding and chips assembly processes were performed on a carrier wafer to overcome warpage associated with conventional Mold-first process. The ultra-thin Fan-out PoP samples pass the reliability include the MST level 3, drop impact test and the Thermal Cycling. It also provides good thermal performance on packaging level and system level applied in mobile device.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"36 1","pages":"21-27"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75184188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kannan Kalappurakal Thankappan, Boris Vaisband, S. Iyer
Electrostatic discharge (ESD) failure results in about 35% of IC field returns, and is the cause of several billiondollar loss to the semiconductor industry. An on-chip ESD detector can help track the electrostatic history of ICs from manufacturing to end-of-life. Two approaches for on-chip ESD detection are presented: variable dielectric width capacitor, and vertical MOSCAP array. The variable dielectric width capacitor approach employs metal plates terminated with sharp corners to enhance local electric field and facilitate easy breakdown of the thin dielectric between the metal plates. The vertical MOSCAP array consists of a capacitor array connected in series. Both approaches were simulated, fabricated, and experimentally characterized in GlobalFoundries 22 nm fully depleted silicon-oninsulator. Vertical MOSCAP arrays detect ESD events starting from ~6 V with 6V granularity, while the variable dielectric width capacitor is suitable for detection of high ESD voltage from 40 V and above.
{"title":"On-Chip ESD Monitor","authors":"Kannan Kalappurakal Thankappan, Boris Vaisband, S. Iyer","doi":"10.1109/ECTC.2019.00-13","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00-13","url":null,"abstract":"Electrostatic discharge (ESD) failure results in about 35% of IC field returns, and is the cause of several billiondollar loss to the semiconductor industry. An on-chip ESD detector can help track the electrostatic history of ICs from manufacturing to end-of-life. Two approaches for on-chip ESD detection are presented: variable dielectric width capacitor, and vertical MOSCAP array. The variable dielectric width capacitor approach employs metal plates terminated with sharp corners to enhance local electric field and facilitate easy breakdown of the thin dielectric between the metal plates. The vertical MOSCAP array consists of a capacitor array connected in series. Both approaches were simulated, fabricated, and experimentally characterized in GlobalFoundries 22 nm fully depleted silicon-oninsulator. Vertical MOSCAP arrays detect ESD events starting from ~6 V with 6V granularity, while the variable dielectric width capacitor is suitable for detection of high ESD voltage from 40 V and above.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"107 1","pages":"2225-2233"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85576140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Khinda, M. Kokash, M. Alhendi, M. Yadav, J. Lombardi, D. Weerawarne, M. Poliks, P. Borgesen, N. Stoffel
Inkjet printing of conducting traces offers well established advantages and disadvantages as an alternative to electroplating of interconnects in flexible electronics. Assessment and optimization of their reliability is, however, often more complicated than commonly recognized. This is the case for an approach based on the deposition of silver nano-particle inks onto mesoporous PET substrates. In this case heating leads the trace resistance to drop not only because of the shrinkage and cure of the organic matrix holding the particles together, but also because some of that matrix 'disappears' into the substrate pores. The substrates can however only sustain relatively brief excursions above their glass transition, nominally 75°C, so it is not always practical to sinter the traces completely by conventional means. That has consequences such as ongoing reductions in resistance over time or under cyclic loading. Laser sintering does however offer the opportunity for much better fusing of the particles without excessive heating of the PET. The present work addresses effects of sintering parameters such as time/temperature and power/speed in oven and laser sintering, respectively, on the initial resistance and its evolution in subsequent low cycle fatigue testing. Interconnects of an average width of 80 µm and thickness of 550 nm were printed and post processed by one of two different sintering techniques: a) Convection oven sintering, and (b) Laser sintering. The resulting resistances were quantified, and samples finally subjected to tensile cycling with amplitudes of 1-2% and in-situ monitoring of the resulting resistance changes using a four-point probe. As expected, the resistance increased in each cycle as the substrate was stretched and it decreased again during unloading. However unlike for other kinds of traces, even though a remaining viscoelastic strain on the substrate prevented the complete elimination of the strain on the trace, the resistance of oven sintered traces usually ended up slightly lower after each cycle than before it. This effect was stronger for higher strain amplitudes, but it could be reduced or eliminated by longer preceding sintering of the traces. While a reduction in resistance may seem preferable to an increase, an even better solution would be a lower initial resistance that remained insensitive to subsequent fatigue cycling. This could be achieved by laser sintering, but careful optimization was required as too low a power did not prevent further resistance drops in cycling while too high ones led to significant degradations in fatigue resistance.
{"title":"Effects of Oven and Laser Sintering Parameters on the Electrical Resistance of IJP Nano-Silver Traces on Mesoporous PET Before and During Fatigue Cycling","authors":"G. Khinda, M. Kokash, M. Alhendi, M. Yadav, J. Lombardi, D. Weerawarne, M. Poliks, P. Borgesen, N. Stoffel","doi":"10.1109/ECTC.2019.00299","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00299","url":null,"abstract":"Inkjet printing of conducting traces offers well established advantages and disadvantages as an alternative to electroplating of interconnects in flexible electronics. Assessment and optimization of their reliability is, however, often more complicated than commonly recognized. This is the case for an approach based on the deposition of silver nano-particle inks onto mesoporous PET substrates. In this case heating leads the trace resistance to drop not only because of the shrinkage and cure of the organic matrix holding the particles together, but also because some of that matrix 'disappears' into the substrate pores. The substrates can however only sustain relatively brief excursions above their glass transition, nominally 75°C, so it is not always practical to sinter the traces completely by conventional means. That has consequences such as ongoing reductions in resistance over time or under cyclic loading. Laser sintering does however offer the opportunity for much better fusing of the particles without excessive heating of the PET. The present work addresses effects of sintering parameters such as time/temperature and power/speed in oven and laser sintering, respectively, on the initial resistance and its evolution in subsequent low cycle fatigue testing. Interconnects of an average width of 80 µm and thickness of 550 nm were printed and post processed by one of two different sintering techniques: a) Convection oven sintering, and (b) Laser sintering. The resulting resistances were quantified, and samples finally subjected to tensile cycling with amplitudes of 1-2% and in-situ monitoring of the resulting resistance changes using a four-point probe. As expected, the resistance increased in each cycle as the substrate was stretched and it decreased again during unloading. However unlike for other kinds of traces, even though a remaining viscoelastic strain on the substrate prevented the complete elimination of the strain on the trace, the resistance of oven sintered traces usually ended up slightly lower after each cycle than before it. This effect was stronger for higher strain amplitudes, but it could be reduced or eliminated by longer preceding sintering of the traces. While a reduction in resistance may seem preferable to an increase, an even better solution would be a lower initial resistance that remained insensitive to subsequent fatigue cycling. This could be achieved by laser sintering, but careful optimization was required as too low a power did not prevent further resistance drops in cycling while too high ones led to significant degradations in fatigue resistance.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"151 1","pages":"1946-1951"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76844850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jin-San Jung, H. Lee, Ji-Min Kim, Yong-Jin Park, Jin Yu, Y. Park, J. Lim, H. Choi, Sung-il Cho, Dong Wook Kim, Sang-ho An
3D packaging technology has been considered as one of the best candidates to improve the system performance by implementing high I/O density as well as providing shortest signal channel path with given package form factor. However, it is difficult to uniformly control the bonding thickness and the precisely align the bumps other than thermo compression (TC) bonding to enable 3D packaging. Moreover, high chip cost and possibly low productivity of TC bonding are main business reasons to prevent this attractive technology from prevailing the mass production environment. To address these well-known technical issues of TC bonding, non-conductive film are proposed for especially high vertical stack with small bump pitch and also minimum chip to chip distance required packages such as high bandwidth memory. In this article, we investigated key process parameters to understand how to optimize bonding process to ensure excellent joint quality for highly dense 3D packages products.
{"title":"A Study of 3D Packaging Interconnection Performance Affected by Thermal Diffusivity and Pressure Transmission","authors":"Jin-San Jung, H. Lee, Ji-Min Kim, Yong-Jin Park, Jin Yu, Y. Park, J. Lim, H. Choi, Sung-il Cho, Dong Wook Kim, Sang-ho An","doi":"10.1109/ECTC.2019.00038","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00038","url":null,"abstract":"3D packaging technology has been considered as one of the best candidates to improve the system performance by implementing high I/O density as well as providing shortest signal channel path with given package form factor. However, it is difficult to uniformly control the bonding thickness and the precisely align the bumps other than thermo compression (TC) bonding to enable 3D packaging. Moreover, high chip cost and possibly low productivity of TC bonding are main business reasons to prevent this attractive technology from prevailing the mass production environment. To address these well-known technical issues of TC bonding, non-conductive film are proposed for especially high vertical stack with small bump pitch and also minimum chip to chip distance required packages such as high bandwidth memory. In this article, we investigated key process parameters to understand how to optimize bonding process to ensure excellent joint quality for highly dense 3D packages products.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"6 1","pages":"204-209"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82203239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xianwen Liang, Jianwen Zhou, Gang Li, T. Zhao, Pengli Zhu, R. Sun, C. Wong
Silver nanowire (AgNW) transparent electrode stands out as a promising candidate to replace indium tin oxide (ITO), whereas the high cost and electromigration of silver ions overshadow the applications of AgNWs in optoelectronics. Copper nanowire (CuNW) is attracting increasing interest and attentions due to its high intrinsic electrical conductivity, earth abundance and lower prince, but the oxidation of CuNW severely prohibits its practical applications, which is an issue to be solved urgently. Herein, nanowelding of CuNWs is achieved via an in-situ redox approach. In this welding process, the copper oxide on the surface of CuNWs as a natural solder is reduced by sodium borohydride (NaBH4) to generate Cu atoms, which selectively aggregate at the intersection of CuNWs and merge the junction owing to the positive site here. The sheet resistance of welded CuNW (W-CuNW) transparent conducting films drop obviously without sacrificing its transmittance, which thereby significantly promotes the optoelectronic performance of the film. Poly(3,4-ethylenedioxythiophene)/poly(styrenesulfonate) (PEDOT:PSS) as a protective layer is coated onto the W-CuNW film to prepare PEDOT:PSS/W-CuNW film. The optoelectronic properties of the PEDOT:PSS/W-CuNW film show excellent stability in ambient atmosphere for 30 days. Beside, no obvious change in the sheet resistance of the PEDOT:PSS/W-CuNW film is observed after 5000 bending cycles under a bending radius of 2 mm, indicating the outstanding mechanical flexibility. Finally, electromagnetic interference (EMI) shielding effectiveness (SE) of the PEDOT:PSS/W-CuNW film is measured within the frequency range from 8.2 GHz to 12.5 GHz. The PEDOT:PSS/W-CuNW film with a EMI SE value above 27 dB and transmittance of 85% underlines the great potential applications in displays, touch panels, airborne optoelectronic pods and aviation camcorders.
{"title":"In-Situ Redox Nanowelding of Copper Nanowires with Surficial Oxide Layer as Solder for Flexible Transparent Electromagnetic Interference Shielding","authors":"Xianwen Liang, Jianwen Zhou, Gang Li, T. Zhao, Pengli Zhu, R. Sun, C. Wong","doi":"10.1109/ECTC.2019.00118","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00118","url":null,"abstract":"Silver nanowire (AgNW) transparent electrode stands out as a promising candidate to replace indium tin oxide (ITO), whereas the high cost and electromigration of silver ions overshadow the applications of AgNWs in optoelectronics. Copper nanowire (CuNW) is attracting increasing interest and attentions due to its high intrinsic electrical conductivity, earth abundance and lower prince, but the oxidation of CuNW severely prohibits its practical applications, which is an issue to be solved urgently. Herein, nanowelding of CuNWs is achieved via an in-situ redox approach. In this welding process, the copper oxide on the surface of CuNWs as a natural solder is reduced by sodium borohydride (NaBH4) to generate Cu atoms, which selectively aggregate at the intersection of CuNWs and merge the junction owing to the positive site here. The sheet resistance of welded CuNW (W-CuNW) transparent conducting films drop obviously without sacrificing its transmittance, which thereby significantly promotes the optoelectronic performance of the film. Poly(3,4-ethylenedioxythiophene)/poly(styrenesulfonate) (PEDOT:PSS) as a protective layer is coated onto the W-CuNW film to prepare PEDOT:PSS/W-CuNW film. The optoelectronic properties of the PEDOT:PSS/W-CuNW film show excellent stability in ambient atmosphere for 30 days. Beside, no obvious change in the sheet resistance of the PEDOT:PSS/W-CuNW film is observed after 5000 bending cycles under a bending radius of 2 mm, indicating the outstanding mechanical flexibility. Finally, electromagnetic interference (EMI) shielding effectiveness (SE) of the PEDOT:PSS/W-CuNW film is measured within the frequency range from 8.2 GHz to 12.5 GHz. The PEDOT:PSS/W-CuNW film with a EMI SE value above 27 dB and transmittance of 85% underlines the great potential applications in displays, touch panels, airborne optoelectronic pods and aviation camcorders.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"115 1","pages":"746-752"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81258600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We have fabricated carbonized polymeric 3-D structures on silica substrate and carbonized them within CMOS operating temperature regime towards obtaining an integrated lab-on-CMOS electrochemical sensor. Metal layers of Ti and Au were deposited on silica substrate to provide electrical contact as well as expedite the formation of electrodes on the substrate. Polymeric conical structures were fabricated on metalized silica substrate using 3-D laser writing based on 2-photon polymerization. Desired carbonization of polymeric structures was obtained using a two step annealing process in oxidative and inert environments. Scanning electron microscopy was used to observe structure morphology and Raman spectroscopy verified carbonization. Finally, electrochemical and impedance characterization of the carbonized electrodes was carried out. Experimental results show the potential of these carbonized electrodes to be used in building low-cost and monolithic CMOS electrochemical sensors.
{"title":"Carbonized Electrodes for Electrochemical Sensing","authors":"M. A. Haque, N. Lavrik, D. Hensley, N. Mcfarlane","doi":"10.1109/ECTC.2019.00-37","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00-37","url":null,"abstract":"We have fabricated carbonized polymeric 3-D structures on silica substrate and carbonized them within CMOS operating temperature regime towards obtaining an integrated lab-on-CMOS electrochemical sensor. Metal layers of Ti and Au were deposited on silica substrate to provide electrical contact as well as expedite the formation of electrodes on the substrate. Polymeric conical structures were fabricated on metalized silica substrate using 3-D laser writing based on 2-photon polymerization. Desired carbonization of polymeric structures was obtained using a two step annealing process in oxidative and inert environments. Scanning electron microscopy was used to observe structure morphology and Raman spectroscopy verified carbonization. Finally, electrochemical and impedance characterization of the carbonized electrodes was carried out. Experimental results show the potential of these carbonized electrodes to be used in building low-cost and monolithic CMOS electrochemical sensors.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"08 1","pages":"2073-2078"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88341494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rapid developments in GaN based µLED mass transfer & assembly have been driven by the demand for high resolution, bright and efficient displays for various solid-state lighting applications. There has however been a roadblock for the commercialization of this technology due to the poor transfer yields attained and high processing costs. The Laser Lift-Off (LLO) process used to release the µLEDs from their native substrate (sapphire) is non-trivial as it can easily crack the chips. In this work, we propose a new µLED transfer and assembly process based on adhesive bonding using a laser de-bondable thermoplastic polyimide (HD3007) that can potentially achieve transfer yields >99%. The LLO process is also done more reliably by using mechanically supported µLEDs which helps to attain nearly 100% LLO yield.
{"title":"High Yield Precision Transfer and Assembly of GaN µLEDs Using Laser Assisted Micro Transfer Printing","authors":"G. Ezhilarasu, A. Hanna, A. Paranjpe, S. Iyer","doi":"10.1109/ECTC.2019.00226","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00226","url":null,"abstract":"Rapid developments in GaN based µLED mass transfer & assembly have been driven by the demand for high resolution, bright and efficient displays for various solid-state lighting applications. There has however been a roadblock for the commercialization of this technology due to the poor transfer yields attained and high processing costs. The Laser Lift-Off (LLO) process used to release the µLEDs from their native substrate (sapphire) is non-trivial as it can easily crack the chips. In this work, we propose a new µLED transfer and assembly process based on adhesive bonding using a laser de-bondable thermoplastic polyimide (HD3007) that can potentially achieve transfer yields >99%. The LLO process is also done more reliably by using mechanically supported µLEDs which helps to attain nearly 100% LLO yield.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"56 1","pages":"1470-1474"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83897878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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