BGA assembly process development for 45nm ELK CUP devices

Abstract

The object of this study is to develop a set of optimized assembly process parameters for BGA package using 45 nm ELK (extreme Low-K) and CUP (circuit under pad) wafer which is driven by high speed and high I/O requested. Due to chip size shrinkage with electrical performance improvement, most of 0.13 mum and 90 nm wafer process technology are moving toward 65 nm and even 45 nm now. The ELK dielectric material for Inter-Level Dielectric (ILD) with the CUP has been designed to get more space for active circuit layout. But the poor mechanical properties of the low-k dielectric and the CUP structure circuit pad design make packaging assembly more challenges. The impacts of IC packaging assembly processes are including the wafer sawing, wire bonding, and molding process. For mass production purpose, the most effective parameters for 45 nm ELK CUP wafer have been studied such as sawing blade type, sawing speed and sawing feeding rate for different wafer thickness, the wire bond time, bond power and bond force. To solve bond wire sweep and mold void issues, the properties of different molding compounds have been studied and assembly process parameters have been optimized. In the end, a real functional die of 45 nm ELK with CUP design has been assembled into package level for reliability test using optimized process parameters.