Pub Date : 2008-08-22DOI: 10.1109/ICEPT.2008.4607126
H. Xi, Minyi Lou, B. An, Fengshun Wu, Yiping Wu
Anti-shock property of lead-free Sn96.5-Ag3.0-Cu0.5 solder bumps was investigated by the high speed impact to explore the relation among the fracture modes and the reflow profile and the microstructure of solder joint. Solder bumps were formed with various reflow profiles and multi-reflow and then subjected to the impact test under a constant speed of 1.8 m/s and a shear standoff of 50 mum. The results show that the IMC status has a close relation with the impact behavior upon one reflow. When the heating factor increases beyond 800 s-degC, the thickness of IMC layer goes up, and the impact absorbed energy of solder bump raises quickly. Upon multi-reflow using the same profile, the IMC thickness changed a little but the failure modes varied a lot.
{"title":"Evaluate anti-shock property of solder bumps by impact test","authors":"H. Xi, Minyi Lou, B. An, Fengshun Wu, Yiping Wu","doi":"10.1109/ICEPT.2008.4607126","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607126","url":null,"abstract":"Anti-shock property of lead-free Sn96.5-Ag3.0-Cu0.5 solder bumps was investigated by the high speed impact to explore the relation among the fracture modes and the reflow profile and the microstructure of solder joint. Solder bumps were formed with various reflow profiles and multi-reflow and then subjected to the impact test under a constant speed of 1.8 m/s and a shear standoff of 50 mum. The results show that the IMC status has a close relation with the impact behavior upon one reflow. When the heating factor increases beyond 800 s-degC, the thickness of IMC layer goes up, and the impact absorbed energy of solder bump raises quickly. Upon multi-reflow using the same profile, the IMC thickness changed a little but the failure modes varied a lot.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"76 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2008-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86053084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607160
Jun Zhang, Y. Lin, Liugang Huang
New interconnect materials are always necessary as a result of evolving packaging technologies and increasing performance and environmental demands on electronic systems. Polymer-based conductive-adhesive materials have become widely used in many electronic packaging interconnect applications. Among all the conductive-adhesive materials, the anisotropic conductive adhesives (ACA) (or anisotropic conductive adhesive films, ACF) have gained popularity as a potential replacement for solder interconnects. For ACF interconnection, thermo-compression (T/C) bonding is the most common method. In this study, the effects of the some important processing parameters, including the increasing rate of bonding temperature and different Teflon films, on the reliability of the ACF joints were investigated. Results show that the performances of the ACF joints were affected by the distribution of conductive particles and the curing degree of the ACF, which was determined by the bonding temperature ramp rates. The bonding strengths of ACF joints are different for the different Teflon filmpsilas thickness and kinds.
{"title":"The effect of the different teflon films on anisotropic conductive adhesive film (ACF) bonding","authors":"Jun Zhang, Y. Lin, Liugang Huang","doi":"10.1109/ICEPT.2008.4607160","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607160","url":null,"abstract":"New interconnect materials are always necessary as a result of evolving packaging technologies and increasing performance and environmental demands on electronic systems. Polymer-based conductive-adhesive materials have become widely used in many electronic packaging interconnect applications. Among all the conductive-adhesive materials, the anisotropic conductive adhesives (ACA) (or anisotropic conductive adhesive films, ACF) have gained popularity as a potential replacement for solder interconnects. For ACF interconnection, thermo-compression (T/C) bonding is the most common method. In this study, the effects of the some important processing parameters, including the increasing rate of bonding temperature and different Teflon films, on the reliability of the ACF joints were investigated. Results show that the performances of the ACF joints were affected by the distribution of conductive particles and the curing degree of the ACF, which was determined by the bonding temperature ramp rates. The bonding strengths of ACF joints are different for the different Teflon filmpsilas thickness and kinds.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"10 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74363025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607018
Zhang Jinyi, Yang Xiaodong, Yang Yi, Zhang Dong, Dong Hui
Shrinks of feature size, high working frequency, and rising number of the IP cores integrated in SOC make the problem with interconnection test critics. A March-CL test for interconnection faults of SOC is proposed in this article. According to the method, eight test patterns are used to detect stuck and delay faults of interconnection between IP cores. The IP connected by interconnection under test (IUT) is wrapped and complied with IEEE1500. Short test time and low area overhead are achieved with the method. Moreover, modified wrapper cell structure with simple control logic is adopted for detecting delay in March-CL test. Finally, March-CL test is applied to ITCpsila02 bench, and result proves that the method covers 100% of stuck, bridge and delay faults in synchronous interconnection test.
{"title":"A March-CL test for interconnection faults of SOC","authors":"Zhang Jinyi, Yang Xiaodong, Yang Yi, Zhang Dong, Dong Hui","doi":"10.1109/ICEPT.2008.4607018","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607018","url":null,"abstract":"Shrinks of feature size, high working frequency, and rising number of the IP cores integrated in SOC make the problem with interconnection test critics. A March-CL test for interconnection faults of SOC is proposed in this article. According to the method, eight test patterns are used to detect stuck and delay faults of interconnection between IP cores. The IP connected by interconnection under test (IUT) is wrapped and complied with IEEE1500. Short test time and low area overhead are achieved with the method. Moreover, modified wrapper cell structure with simple control logic is adopted for detecting delay in March-CL test. Finally, March-CL test is applied to ITCpsila02 bench, and result proves that the method covers 100% of stuck, bridge and delay faults in synchronous interconnection test.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"31 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77368941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607148
Xiaoqin Lin, L. Luo
Due to the advantages of small-footprint, short-lead, high performance, high-packaging-density and thin profile, flip-chip-on-board (FCOB) technology is becoming an attractive choice in todaypsilas high density electronic packaging industry. With the trend toward lead-free and miniaturization in consumer electronics, the fatigue reliability of the small size lead-free FC solder joint on low cost PCB substrate are becoming one of the important issues. In this study, the reliability of sub 100 microns Sn-3.0Ag flip chip solder bump on FR4 substrate was investigated under thermal cycling between -40degC to 125degC. The influences of the shape of solder joint on the failed plane and the fatigue life were studied. The failed plane of the solder joint was discussed by the stress state analysis of the solder joint. Using the metallography, SEM, and live testing of the resistance, failure character and failure mechanism of the solder joint before and after underfilling were analyzed. The increasement of the fatigue life with the use of underfill was interpreted by plastic mechanics.
{"title":"The reliability study of sub 100 microns SnAg flip chip solder bump on FR4 substrate under thermal cycling","authors":"Xiaoqin Lin, L. Luo","doi":"10.1109/ICEPT.2008.4607148","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607148","url":null,"abstract":"Due to the advantages of small-footprint, short-lead, high performance, high-packaging-density and thin profile, flip-chip-on-board (FCOB) technology is becoming an attractive choice in todaypsilas high density electronic packaging industry. With the trend toward lead-free and miniaturization in consumer electronics, the fatigue reliability of the small size lead-free FC solder joint on low cost PCB substrate are becoming one of the important issues. In this study, the reliability of sub 100 microns Sn-3.0Ag flip chip solder bump on FR4 substrate was investigated under thermal cycling between -40degC to 125degC. The influences of the shape of solder joint on the failed plane and the fatigue life were studied. The failed plane of the solder joint was discussed by the stress state analysis of the solder joint. Using the metallography, SEM, and live testing of the resistance, failure character and failure mechanism of the solder joint before and after underfilling were analyzed. The increasement of the fatigue life with the use of underfill was interpreted by plastic mechanics.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"8 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85617102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607054
Fangjuan Qi, Li Sun, Zhezhe Hou, Jianqiang Wang, C. Qin
In this article, the effects of Ni nanoparticles addition on shear property and microstructure of Sn-3.5Ag Lead-free solder joint was studied. The nickel nano-composite Sn-3.5Ag solder was prepared by adding dispersant to the dry nanoparticles and mechanically stirred Ni nanoparticles into the Sn-3.5Ag Lead-free solder paste. The shear force of the Sn-3.5Ag solder, 0.5 and 1.0 wt% nickel nano-composite solder was tested respectively at reflow 120s and 240s. The result shows that adding nickel nanoparticles can improve the shear performance of the soldered joint; the shear force of the soldered joint is highest when adding 0.5 wt% Ni nanoparticles at reflow 240s. The SEM observations shows that the hexagonal Cu6Sn5 IMC (intermetallic compound) in the inside solder is disappears gradually and the morphsa of the IMC that on the interface of the solder joint becomes planar after adding Ni nanoparticles into solder.
{"title":"The effects of Ni nanoparticles addition on shear behavior and microstructure of Sn-Ag Lead-free solder","authors":"Fangjuan Qi, Li Sun, Zhezhe Hou, Jianqiang Wang, C. Qin","doi":"10.1109/ICEPT.2008.4607054","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607054","url":null,"abstract":"In this article, the effects of Ni nanoparticles addition on shear property and microstructure of Sn-3.5Ag Lead-free solder joint was studied. The nickel nano-composite Sn-3.5Ag solder was prepared by adding dispersant to the dry nanoparticles and mechanically stirred Ni nanoparticles into the Sn-3.5Ag Lead-free solder paste. The shear force of the Sn-3.5Ag solder, 0.5 and 1.0 wt% nickel nano-composite solder was tested respectively at reflow 120s and 240s. The result shows that adding nickel nanoparticles can improve the shear performance of the soldered joint; the shear force of the soldered joint is highest when adding 0.5 wt% Ni nanoparticles at reflow 240s. The SEM observations shows that the hexagonal Cu6Sn5 IMC (intermetallic compound) in the inside solder is disappears gradually and the morphsa of the IMC that on the interface of the solder joint becomes planar after adding Ni nanoparticles into solder.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"2 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81972097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607005
Zongyuan Liu, Sheng Liu, Kai Wang, Xiaobing Luo
The state of phosphor will greatly influence the packaging performance such as luminous efficiency, quality of white light and color uniformity. The analysis presents that the small variations of thickness and concentration could significantly influence the light extraction efficiency and the correlated color temperature (CCT). With the increase of thickness and concentration, the light extraction efficiency is reduced, and the yellow blue ratio is increased, which means the color will tend to be warm white or yellow light. The reflector has slight influence on the performance, and the remote phosphor location is a better choice in packaging. When the thickness and concentration are determined, the manufacture tolerance for the variation are in the range of plusmn 0.02 mm for thickness and plusmn 5 mm-1 for concentration.
{"title":"Effects of phosphor’s thickness and concentration on performance of white LEDs","authors":"Zongyuan Liu, Sheng Liu, Kai Wang, Xiaobing Luo","doi":"10.1109/ICEPT.2008.4607005","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607005","url":null,"abstract":"The state of phosphor will greatly influence the packaging performance such as luminous efficiency, quality of white light and color uniformity. The analysis presents that the small variations of thickness and concentration could significantly influence the light extraction efficiency and the correlated color temperature (CCT). With the increase of thickness and concentration, the light extraction efficiency is reduced, and the yellow blue ratio is increased, which means the color will tend to be warm white or yellow light. The reflector has slight influence on the performance, and the remote phosphor location is a better choice in packaging. When the thickness and concentration are determined, the manufacture tolerance for the variation are in the range of plusmn 0.02 mm for thickness and plusmn 5 mm-1 for concentration.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"23 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82513435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607136
C.Y. Lin, Y. Chen, G. Shen, D. Liu, C. Kuo, C.L. Hsu
The aim of this research is to investigate the mechanical behavior of lead-free solder for high speed impact. A high speed impact test was set up to measure the solder joint reliability. Differential impact speed and room temperature aging effect has been studied with Ni/Au substrate. Furthermore, two different solder alloys (96.5Sn-3Ag-0.5Cu, 98.5Sn-1Ag-0.5C) and three different reflow profiles are considered. This paper focuses on failure mode analysis and investigates the failure characteristics of lead-free solder joints, 96.5Sn-3Ag-0.5Cu and 98.5Sn-1Ag- 0.5C, which are aging at room temperature, respectively, then those solder are impacted at shear rates of 0.3 m/s and 1.0 m/s. Four types of failure mode are found in this high speed impact testing result. Mode M1 is the fracture around the interface but not remain the solder on pad. Mode M2 is fracture around the interface and remained the solder on pad. Mode M3 is fracture across the solder ball. Mode M4 is fracture on the substrate with lift the pad. The aging time could increase the interfacial strength, therefore the percentage of M3 and M4 mode failures increases in Ni/Au substrate. According the results, we find that in reflow profile A and reflow profile C, the failure percentage of Mode M2 is increasing; in reflow profile B, the failure percentage of Mode M3 and Mode M4 are large than Mode M1 and Mode M2.The failure mode M2 is the majority in solder alloy 96.5Sn-3Ag- 0.5Cu, and the failure mode M2 and M3 are the majority in solder alloy 98.5Sn-1Ag-0.5C.
{"title":"Failure mode analysis of lead-free solder joints under differential reflow profiles by high speed impact testing","authors":"C.Y. Lin, Y. Chen, G. Shen, D. Liu, C. Kuo, C.L. Hsu","doi":"10.1109/ICEPT.2008.4607136","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607136","url":null,"abstract":"The aim of this research is to investigate the mechanical behavior of lead-free solder for high speed impact. A high speed impact test was set up to measure the solder joint reliability. Differential impact speed and room temperature aging effect has been studied with Ni/Au substrate. Furthermore, two different solder alloys (96.5Sn-3Ag-0.5Cu, 98.5Sn-1Ag-0.5C) and three different reflow profiles are considered. This paper focuses on failure mode analysis and investigates the failure characteristics of lead-free solder joints, 96.5Sn-3Ag-0.5Cu and 98.5Sn-1Ag- 0.5C, which are aging at room temperature, respectively, then those solder are impacted at shear rates of 0.3 m/s and 1.0 m/s. Four types of failure mode are found in this high speed impact testing result. Mode M1 is the fracture around the interface but not remain the solder on pad. Mode M2 is fracture around the interface and remained the solder on pad. Mode M3 is fracture across the solder ball. Mode M4 is fracture on the substrate with lift the pad. The aging time could increase the interfacial strength, therefore the percentage of M3 and M4 mode failures increases in Ni/Au substrate. According the results, we find that in reflow profile A and reflow profile C, the failure percentage of Mode M2 is increasing; in reflow profile B, the failure percentage of Mode M3 and Mode M4 are large than Mode M1 and Mode M2.The failure mode M2 is the majority in solder alloy 96.5Sn-3Ag- 0.5Cu, and the failure mode M2 and M3 are the majority in solder alloy 98.5Sn-1Ag-0.5C.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"30 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87103609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607026
Yingliang Li, Jide-Zhao
OFDM (orthogonal frequency division multiplex) mobile communication system is so popular in recent because it has so many virtues as effective frequency spectrum, wide-band, high speed rate, etc. But it has so many challenges in technical field, such as the high efficiency of PA (power amplifier) and linearity. RF (radio frequency) amplifier with ET (envelop-tracing) structure is described for OFDM systems in this paper. The first study the ET amplifier model, and then a high-efficiency OFDM amplifier is presented with GaN HEMT (heterostrucutre field-effect transistors), and includes the theoretic analysis and circuit design. Finally, the design circuit is simulated by ADS (advanced design systems) software, and gets the average DE (drains efficiency) of the amplifier is as high as 50% for an OFDM (Wimax) modulated signal with EVM of 2.94% at an average output power of 50 W and gain of 13.0 dB from simulating result. The design has good efficiency and linearity. All of these performances are satisfied with the OFDM systempsilas requirement of RF. This design may be applied for the OFDM systems compare with the standard of OFDM.
{"title":"A novel high effective envelope-tracking amplifier for OFDM systems","authors":"Yingliang Li, Jide-Zhao","doi":"10.1109/ICEPT.2008.4607026","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607026","url":null,"abstract":"OFDM (orthogonal frequency division multiplex) mobile communication system is so popular in recent because it has so many virtues as effective frequency spectrum, wide-band, high speed rate, etc. But it has so many challenges in technical field, such as the high efficiency of PA (power amplifier) and linearity. RF (radio frequency) amplifier with ET (envelop-tracing) structure is described for OFDM systems in this paper. The first study the ET amplifier model, and then a high-efficiency OFDM amplifier is presented with GaN HEMT (heterostrucutre field-effect transistors), and includes the theoretic analysis and circuit design. Finally, the design circuit is simulated by ADS (advanced design systems) software, and gets the average DE (drains efficiency) of the amplifier is as high as 50% for an OFDM (Wimax) modulated signal with EVM of 2.94% at an average output power of 50 W and gain of 13.0 dB from simulating result. The design has good efficiency and linearity. All of these performances are satisfied with the OFDM systempsilas requirement of RF. This design may be applied for the OFDM systems compare with the standard of OFDM.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"16 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89132220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
More and more high-speed data transmission formats such as rapid IO, hyper transport, Gigabit Ethernet, Serial ATA etc. are becoming prevalent. As substrate interconnection density and channel data rate are getting increasingly higher, various 3D effects, crosstalk, and discontinuity - induced ISI are playing a much more important role, for both signal channels and power distribution networks . The substrate interconnection structures are becoming the major bandwidth constraint for most of the package designer. As data rates continue to increase, transitioning to solder bump or Au stud bump flip-chip interconnects or low-loss substrate materials results in excessive cost. It is therefore increasingly important to provide a high performance and low-cost packaging solution. The aim of this paper is to proposal a design solution of normal plastic ball grid array (PBGA) package for high speed devices. The electrical simulation method of the effects of variation of package design parameters such as signal path structure, wire bonding, through hole via, ball placement tactic and plating stub are highlighted. The conclusion of this paper is recommendation for high-speed package electrical design.
{"title":"High speed package design and electrical performance analysis","authors":"Shu-Qiang Zhang, Hung-Hsiang Cheng, Yin-Guang Zheng, Chang-Lin Yeh","doi":"10.1109/ICEPT.2008.4606973","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606973","url":null,"abstract":"More and more high-speed data transmission formats such as rapid IO, hyper transport, Gigabit Ethernet, Serial ATA etc. are becoming prevalent. As substrate interconnection density and channel data rate are getting increasingly higher, various 3D effects, crosstalk, and discontinuity - induced ISI are playing a much more important role, for both signal channels and power distribution networks . The substrate interconnection structures are becoming the major bandwidth constraint for most of the package designer. As data rates continue to increase, transitioning to solder bump or Au stud bump flip-chip interconnects or low-loss substrate materials results in excessive cost. It is therefore increasingly important to provide a high performance and low-cost packaging solution. The aim of this paper is to proposal a design solution of normal plastic ball grid array (PBGA) package for high speed devices. The electrical simulation method of the effects of variation of package design parameters such as signal path structure, wire bonding, through hole via, ball placement tactic and plating stub are highlighted. The conclusion of this paper is recommendation for high-speed package electrical design.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"53 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84707920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606969
Q. Fei, Wang Yngve, Liu Bin, An Tong, J. Ling
4-point dynamic bending tests of board level electronic packages were carried out in order to investigate the reliability of solder joints. A high speed camera and the digital image correlation method were used to measure the deflection of the PCB board. A finite element model to simulate the test was built up and was validated by the test data. A parameter study was subsequently implemented. The results show that at certain value of PCB stiffness the peeling stress reaches its peak. The package installation angel has significant effect on the peeling stress of the solder joints.
{"title":"Dynamic bending tests and numerical simulation of board level electronic package","authors":"Q. Fei, Wang Yngve, Liu Bin, An Tong, J. Ling","doi":"10.1109/ICEPT.2008.4606969","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606969","url":null,"abstract":"4-point dynamic bending tests of board level electronic packages were carried out in order to investigate the reliability of solder joints. A high speed camera and the digital image correlation method were used to measure the deflection of the PCB board. A finite element model to simulate the test was built up and was validated by the test data. A parameter study was subsequently implemented. The results show that at certain value of PCB stiffness the peeling stress reaches its peak. The package installation angel has significant effect on the peeling stress of the solder joints.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"16 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88190920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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