A. Nakajima, Q. Khosru, T. Yoshirnoto, T. Kidera, S. Yokoyama
{"title":"Soft breakdown free atomic-layer-deposited silicon-nitride/SiO/sub 2/ stack gate dielectrics","authors":"A. Nakajima, Q. Khosru, T. Yoshirnoto, T. Kidera, S. Yokoyama","doi":"10.1109/IEDM.2001.979450","DOIUrl":null,"url":null,"abstract":"An extremely-thin (0.3-0.4 nm) silicon nitride layer has been deposited on thermally grown SiO/sub 2/ by an atomic-layer-deposition (ALD) technique. The boron penetration through the stack gate dielectrics has been dramatically suppressed and the reliability has been significantly improved. An exciting feature of no soft breakdown (SBD) events is observed in ramped voltage stressing and time-dependent dielectric breakdown (TDDB) characteristics. A model has been proposed, which consistently explains the no-SBD phenomena in ALD-silicon-nitride/SiO/sub 2/ stack gate dielectrics as well as the SBD events in conventional SiO/sub 2/ dielectrics.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"5 1","pages":"6.5.1-6.5.4"},"PeriodicalIF":0.0000,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2001.979450","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
An extremely-thin (0.3-0.4 nm) silicon nitride layer has been deposited on thermally grown SiO/sub 2/ by an atomic-layer-deposition (ALD) technique. The boron penetration through the stack gate dielectrics has been dramatically suppressed and the reliability has been significantly improved. An exciting feature of no soft breakdown (SBD) events is observed in ramped voltage stressing and time-dependent dielectric breakdown (TDDB) characteristics. A model has been proposed, which consistently explains the no-SBD phenomena in ALD-silicon-nitride/SiO/sub 2/ stack gate dielectrics as well as the SBD events in conventional SiO/sub 2/ dielectrics.