Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979400
J. Hergenrother, G. Wilk, T. Nigam, F. Klemens, D. Monroe, P. Silverman, T. Sorsch, B. Busch, M. Green, M. R. Baker, T. Boone, M. Bude, N. A. Ciampa, E. Ferry, A. Fiory, S. Hillenius, D. Jacobson, R.W. Johnson, P. Kalavade, R. Keller, C. King, A. Kornblit, H. Krautter, J.T.-C. Lee, W. Mansfield, J. Miner, M. Morris, S. Oh, J. Rosamilia, B. Sapjeta, K. Short, K. Steiner, D. Muller, P. Voyles, J. Grazul, E. Shero, M. Givens, C. Pomarede, M. Mazanec, C. Werkhoven
We have integrated HfO/sub 2/ and Al/sub 2/O/sub 3/ gate dielectrics grown by atomic layer chemical vapor deposition (ALD) with poly-Si gate electrodes in the vertical replacement-gate (VRG) MOSFET geometry. These transistors are among the first reported with ALD HfO/sub 2/ gate dielectrics, and have HfO/sub 2/ target equivalent oxide thicknesses (tEOT's) down to 13 /spl Aring/. The poly-crystalline HfO/sub 2/ films in these VRG nMOSFETs exhibit extremely low gate leakage (GL) current densities of J/sub G/ /spl sim/ 10/sup -7/ A/cm/sup 2/ at V/sub G/-V/sub T,Long/ = 0.6 V for 15 /spl Aring/ tEOT devices. This indicates that amorphous gate dielectrics may not be necessary to meet GL requirements. HfO/sub 2/ devices with 50 nm gate length L/sub G/ exhibit drive currents [normalized by the coded width W/sub C/] of 490 /spl mu/A//spl mu/m for 1 V operation (overdrive V/sub GS/-V/sub T/ = 0.6 V) with good short-channel performance. These results demonstrate that ALD is compatible with the demanding VRG geometry, thereby illustrating that it should be well-suited to essentially any novel device structure built with Si-compatible materials.
{"title":"50 nm vertical replacement-gate (VRG) nMOSFETs with ALD HfO/sub 2/ and Al/sub 2/O/sub 3/ gate dielectrics","authors":"J. Hergenrother, G. Wilk, T. Nigam, F. Klemens, D. Monroe, P. Silverman, T. Sorsch, B. Busch, M. Green, M. R. Baker, T. Boone, M. Bude, N. A. Ciampa, E. Ferry, A. Fiory, S. Hillenius, D. Jacobson, R.W. Johnson, P. Kalavade, R. Keller, C. King, A. Kornblit, H. Krautter, J.T.-C. Lee, W. Mansfield, J. Miner, M. Morris, S. Oh, J. Rosamilia, B. Sapjeta, K. Short, K. Steiner, D. Muller, P. Voyles, J. Grazul, E. Shero, M. Givens, C. Pomarede, M. Mazanec, C. Werkhoven","doi":"10.1109/IEDM.2001.979400","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979400","url":null,"abstract":"We have integrated HfO/sub 2/ and Al/sub 2/O/sub 3/ gate dielectrics grown by atomic layer chemical vapor deposition (ALD) with poly-Si gate electrodes in the vertical replacement-gate (VRG) MOSFET geometry. These transistors are among the first reported with ALD HfO/sub 2/ gate dielectrics, and have HfO/sub 2/ target equivalent oxide thicknesses (tEOT's) down to 13 /spl Aring/. The poly-crystalline HfO/sub 2/ films in these VRG nMOSFETs exhibit extremely low gate leakage (GL) current densities of J/sub G/ /spl sim/ 10/sup -7/ A/cm/sup 2/ at V/sub G/-V/sub T,Long/ = 0.6 V for 15 /spl Aring/ tEOT devices. This indicates that amorphous gate dielectrics may not be necessary to meet GL requirements. HfO/sub 2/ devices with 50 nm gate length L/sub G/ exhibit drive currents [normalized by the coded width W/sub C/] of 490 /spl mu/A//spl mu/m for 1 V operation (overdrive V/sub GS/-V/sub T/ = 0.6 V) with good short-channel performance. These results demonstrate that ALD is compatible with the demanding VRG geometry, thereby illustrating that it should be well-suited to essentially any novel device structure built with Si-compatible materials.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"71 1","pages":"3.1.1-3.1.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73760214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1007/978-3-7091-6244-6_3
M. Hane, T. Ikezawa, K. Takeuchi, G. Gilmer
{"title":"Monte Carlo impurity diffusion simulation considering charged species for low thermal budget sub-50 nm CMOS process modeling","authors":"M. Hane, T. Ikezawa, K. Takeuchi, G. Gilmer","doi":"10.1007/978-3-7091-6244-6_3","DOIUrl":"https://doi.org/10.1007/978-3-7091-6244-6_3","url":null,"abstract":"","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"84 1","pages":"38.4.1-38.4.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74091778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979463
N. Okamoto, T. Takahashi, K. Imanishi, K. Sawada, N. Hara
Demonstrated InP-based HEMTs without drain conductance (g/sub d/) frequency dispersion for broadband optical communication systems. It was possible to markedly suppress the g/sub d/ dispersion by using composite channel and double-doped structures rather than a conventional HEMT structure. Furthermore, we clarified that hole generation time by impact ionization determines the frequency range of the g/sub d/ dispersion in a conventional InP-based HEMT by investigating the g/sub d/ dispersion over a wide range of frequencies (100 Hz-20 GHz).
{"title":"Suppression of drain conductance dispersion in InP-based HEMTs for broadband optical communication systems","authors":"N. Okamoto, T. Takahashi, K. Imanishi, K. Sawada, N. Hara","doi":"10.1109/IEDM.2001.979463","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979463","url":null,"abstract":"Demonstrated InP-based HEMTs without drain conductance (g/sub d/) frequency dispersion for broadband optical communication systems. It was possible to markedly suppress the g/sub d/ dispersion by using composite channel and double-doped structures rather than a conventional HEMT structure. Furthermore, we clarified that hole generation time by impact ionization determines the frequency range of the g/sub d/ dispersion in a conventional InP-based HEMT by investigating the g/sub d/ dispersion over a wide range of frequencies (100 Hz-20 GHz).","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"83 1","pages":"9.1.1-9.1.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74131010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979565
Min Yang, Jeremy D. Schaub, Dennis L. Rogers, M. B. Ritter, K. Rim, J. J. Welser, Byeongju Park
Lateral trench photodetectors (LTD) on silicon-on-insulator (SOI) have been fabricated using a fully CMOS compatible process. High speed (2.0 GHz), high quantum efficiency (51%), and excellent frequency response characteristics have been achieved at 851 nm with a supply voltage of only 3.3 V.
{"title":"High speed silicon lateral trench detector on SOI substrate","authors":"Min Yang, Jeremy D. Schaub, Dennis L. Rogers, M. B. Ritter, K. Rim, J. J. Welser, Byeongju Park","doi":"10.1109/IEDM.2001.979565","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979565","url":null,"abstract":"Lateral trench photodetectors (LTD) on silicon-on-insulator (SOI) have been fabricated using a fully CMOS compatible process. High speed (2.0 GHz), high quantum efficiency (51%), and excellent frequency response characteristics have been achieved at 851 nm with a supply voltage of only 3.3 V.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"99 1","pages":"24.1.1-24.1.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74376400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979608
D. Ielmini, A. Spinelli, A. Lacaita, A. Modelli
A new physically-based model for reliability analysis of flash memories is presented. The model provides a quantitative description of the distribution of the stress-induced leakage current (SILC) in large memory arrays, considering the statistics of the defects responsible for the trap-assisted tunneling (TAT) current. Simulation results are in good agreement with SILC statistics over oxide thicknesses of 6.5, 8.8 and 9.7 nm. The model can be used to quantitatively evaluate the failure rate under different conditions and assess the trade-off between oxide thinning and device reliability. The relationship between tunnel oxide scalability and defect concentration is also quantitatively assessed.
{"title":"Statistical modeling of reliability and scaling projections for flash memories","authors":"D. Ielmini, A. Spinelli, A. Lacaita, A. Modelli","doi":"10.1109/IEDM.2001.979608","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979608","url":null,"abstract":"A new physically-based model for reliability analysis of flash memories is presented. The model provides a quantitative description of the distribution of the stress-induced leakage current (SILC) in large memory arrays, considering the statistics of the defects responsible for the trap-assisted tunneling (TAT) current. Simulation results are in good agreement with SILC statistics over oxide thicknesses of 6.5, 8.8 and 9.7 nm. The model can be used to quantitatively evaluate the failure rate under different conditions and assess the trade-off between oxide thinning and device reliability. The relationship between tunnel oxide scalability and defect concentration is also quantitatively assessed.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"8 1","pages":"32.2.1-32.2.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75408186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979561
S. Purushothaman, S. Nitta, J. G. Ryan, C. Narayan, M. Krishnan, S. Cohen, S. Gates, S. Whitehair, J. Hedrick, C. Tyberg, S. Greco, K. Rodbell, E. Huang, T. Dalton, R. Dellaguardia, K. Saenger, E. Simonyi, S.T. Chen, K. Malone, R. Miller, W. Volksen
In this paper, we discuss the challenges associated with producing, characterizing and integrating porous dielectrics into back-end-of-line (BEOL) interconnects and present results from our integration evaluations.
{"title":"Opportunities and challenges in ultra low k dielectrics for interconnect applications","authors":"S. Purushothaman, S. Nitta, J. G. Ryan, C. Narayan, M. Krishnan, S. Cohen, S. Gates, S. Whitehair, J. Hedrick, C. Tyberg, S. Greco, K. Rodbell, E. Huang, T. Dalton, R. Dellaguardia, K. Saenger, E. Simonyi, S.T. Chen, K. Malone, R. Miller, W. Volksen","doi":"10.1109/IEDM.2001.979561","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979561","url":null,"abstract":"In this paper, we discuss the challenges associated with producing, characterizing and integrating porous dielectrics into back-end-of-line (BEOL) interconnects and present results from our integration evaluations.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"14 1","pages":"23.2.1-23.2.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75858710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979589
F. Boeuf, T. Skotnicki, S. Monfray, C. Julien, D. Dutartre, J. Martins, P. Mazoyer, R. Palla, B. Tavel, P. Ribot, E. Søndergård, A. Sanquer
In nanometer MOSFETs, because of the small channel size, mesoscopic and even quantum effects can come into play. We have fabricated l6 nm NMOS devices featuring I/sub on/=400 /spl mu/A//spl mu/m and I/sub off/=0.8 /spl mu/A//spl mu/m and demonstrate that the FET principle is still confirmed at room temperature. We have deliberately used a non-overlapped SD/gate architecture, showing that, with adapted channel doping, it not only performs equally as well as the overlapped one, but also shows 1000/spl times/ reduced dispersion and is easily manufacturable. Finally, we show that quantization of energy in the channel motivates a study of performance at low temperature, and that the leading effect at low temperature and low voltage is Coulomb blockade.
{"title":"16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation","authors":"F. Boeuf, T. Skotnicki, S. Monfray, C. Julien, D. Dutartre, J. Martins, P. Mazoyer, R. Palla, B. Tavel, P. Ribot, E. Søndergård, A. Sanquer","doi":"10.1109/IEDM.2001.979589","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979589","url":null,"abstract":"In nanometer MOSFETs, because of the small channel size, mesoscopic and even quantum effects can come into play. We have fabricated l6 nm NMOS devices featuring I/sub on/=400 /spl mu/A//spl mu/m and I/sub off/=0.8 /spl mu/A//spl mu/m and demonstrate that the FET principle is still confirmed at room temperature. We have deliberately used a non-overlapped SD/gate architecture, showing that, with adapted channel doping, it not only performs equally as well as the overlapped one, but also shows 1000/spl times/ reduced dispersion and is easily manufacturable. Finally, we show that quantization of energy in the channel motivates a study of performance at low temperature, and that the leading effect at low temperature and low voltage is Coulomb blockade.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"113 1","pages":"29.5.1-29.5.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73227438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979634
M.Y. Yang, S.B. Chen, A. Chin, C. Sun, B. Lan, S. Chen
We have compared the memory performance of one-transistor ferroelectric MOSFET (FeMOSFET) with stacked Pb(Zr,Ti)O/sub 3/ (PZT), SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT), and Bi/sub 3.75/La/sub 0.25/Ti/sub 3/O/sub 12/ (BLT)/40 /spl Aring/-Al/sub 2/O/sub 3/ gate dielectrics. The SBT/Al/sub 2/O/sub 3/ FeMOSFET has the largest I/sub ON//I/sub OFF/ of greater than 2 orders of magnitude, and the PZT/Al/sub 2/O/sub 3/ FeMOSFET has the fast 10 ns program/erase time, >10/sup 11/ program/erase endurance, and 10 years retention.
{"title":"One-transistor PZT/Al/sub 2/O/sub 3/, SBT/Al/sub 2/O/sub 3/ and BLT/Al/sub 2/O/sub 3/ stacked gate memory","authors":"M.Y. Yang, S.B. Chen, A. Chin, C. Sun, B. Lan, S. Chen","doi":"10.1109/IEDM.2001.979634","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979634","url":null,"abstract":"We have compared the memory performance of one-transistor ferroelectric MOSFET (FeMOSFET) with stacked Pb(Zr,Ti)O/sub 3/ (PZT), SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT), and Bi/sub 3.75/La/sub 0.25/Ti/sub 3/O/sub 12/ (BLT)/40 /spl Aring/-Al/sub 2/O/sub 3/ gate dielectrics. The SBT/Al/sub 2/O/sub 3/ FeMOSFET has the largest I/sub ON//I/sub OFF/ of greater than 2 orders of magnitude, and the PZT/Al/sub 2/O/sub 3/ FeMOSFET has the fast 10 ns program/erase time, >10/sup 11/ program/erase endurance, and 10 years retention.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"42 1","pages":"36.3.1-36.3.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80163289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979635
K. Tsuji, K. Suemitsu, T. Mukai, K. Nagahara, H. Masubuchi, H. Utsumi, K. Kikuta
0.1 /spl mu/m rule magnetic random access memory (MRAM) was developed using double-layered hard mask of SiO/sub 2//metal. 30% magnetoresistance ratio under switching operation, read and write characteristics for MRAM cell with 0.1/spl times/0.6 /spl mu/m/sup 2/ were observed using current induced magnetic field. It is found that switching current of tunneling magnetoresistance (TMR) device with 0.1 /spl mu/m length can be reduced by thinning free layer and reduction of TMR aspect ratio.
{"title":"0.1 /spl mu/m-rule MRAM development using double-layered hard mask","authors":"K. Tsuji, K. Suemitsu, T. Mukai, K. Nagahara, H. Masubuchi, H. Utsumi, K. Kikuta","doi":"10.1109/IEDM.2001.979635","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979635","url":null,"abstract":"0.1 /spl mu/m rule magnetic random access memory (MRAM) was developed using double-layered hard mask of SiO/sub 2//metal. 30% magnetoresistance ratio under switching operation, read and write characteristics for MRAM cell with 0.1/spl times/0.6 /spl mu/m/sup 2/ were observed using current induced magnetic field. It is found that switching current of tunneling magnetoresistance (TMR) device with 0.1 /spl mu/m length can be reduced by thinning free layer and reduction of TMR aspect ratio.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"7 1","pages":"36.4.1-36.4.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79028281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979394
Jungdal Choi, Seong-Soon Cho, Y. Yim, Jaeduk Lee, H. Kim, Kyung-joong Joo, S. Hur, Heung-Soo Im, Joon Kim, Jeong-Woo Lee, K. Seo, M. Kang, Kyungryun Kim, Jeong-Lim Nam, Kyucharn Park, Moon-Yong Lee
An 1 Gb NAND flash memory has been successfully developed by integrating new technologies, inverse narrow-width effect (INWE) suppression scheme, 32-cell NAND flash combined with the scaling-down of tunnel oxide, inter-poly ONO, and gate poly re-oxidation. It is implemented using KrF photolithography along with a resolution enhancing technique, the planarized surface by etch-back and CMP processes, highly selective contact etching and nonoverlapped dual damascene metallization. Thus, for the first time, a 1 Gb NAND flash memory with mass-producible chip size of 132 mm/sup 2/, lower Vcc operation below 1.8 V and lower power consumption, has been obtained.
{"title":"Highly manufacturable 1 Gb NAND flash using 0.12 /spl mu/m process technology","authors":"Jungdal Choi, Seong-Soon Cho, Y. Yim, Jaeduk Lee, H. Kim, Kyung-joong Joo, S. Hur, Heung-Soo Im, Joon Kim, Jeong-Woo Lee, K. Seo, M. Kang, Kyungryun Kim, Jeong-Lim Nam, Kyucharn Park, Moon-Yong Lee","doi":"10.1109/IEDM.2001.979394","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979394","url":null,"abstract":"An 1 Gb NAND flash memory has been successfully developed by integrating new technologies, inverse narrow-width effect (INWE) suppression scheme, 32-cell NAND flash combined with the scaling-down of tunnel oxide, inter-poly ONO, and gate poly re-oxidation. It is implemented using KrF photolithography along with a resolution enhancing technique, the planarized surface by etch-back and CMP processes, highly selective contact etching and nonoverlapped dual damascene metallization. Thus, for the first time, a 1 Gb NAND flash memory with mass-producible chip size of 132 mm/sup 2/, lower Vcc operation below 1.8 V and lower power consumption, has been obtained.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"14 1","pages":"2.1.1-2.1.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85241777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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