A high data rate BPSK receiver implementation in FPGA for high dynamics applications

2011 VII Southern Conference on Programmable Logic (SPL) Pub Date : 2011-04-13 DOI:10.1109/SPL.2011.5782654

Juan Augusto Maya, Nicolas A. Casco, P. A. Roncagliolo, Javier G. García

引用次数: 4

Abstract

In this paper we present the implementation of a FPGA based high data rate BPSK receiver specifically designed to withstand the high dynamics of airborne vehicles (i.e. aircraft, sounding rockets, satellites, etc.). The carrier recovery is implemented through a Costas loop, and a Gardner detector is used for the timing recovery. This architecture was chosen because it provides almost independent carrier and bit synchronization. Loop filters were designed through analog to discrete-time conversion. A theoretical analysis of the design, simulation and its implementation is presented.

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高数据速率BPSK接收机的FPGA实现，用于高动态应用

在本文中，我们提出了一种基于FPGA的高数据速率BPSK接收机的实现，该接收机专门设计用于承受机载飞行器(即飞机，探空火箭，卫星等)的高动态。载波恢复通过Costas环路实现，Gardner检测器用于定时恢复。之所以选择这种体系结构，是因为它提供了几乎独立的载波和位同步。通过模拟时间到离散时间的转换，设计了环路滤波器。对该系统的设计、仿真和实现进行了理论分析。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2011 VII Southern Conference on Programmable Logic (SPL)

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