FPGA implementation of two very low complexity LDPC decoders

2011 VII Southern Conference on Programmable Logic (SPL) Pub Date : 2011-04-13 DOI:10.1109/SPL.2011.5782617

J. Castiñeira Moreira, M. Rabini, C. Gonzalez, C. A. Gayoso, L. Arnone

引用次数: 2

Abstract

Low-Density Parity-Check (LDPC) codes are very efficient error control codes that are being considered as part of many next generation communication systems. In this paper FPGA implementations of two low complexity decoders are presented. These two implementations operate over any kind of parity check matrix, (including those randomly generated, structurally generated, either systematic or non systematic) and can be parametrically performed for any code rate k/n. The proposed implementations are both of very low complexity, because they operate using only sums, subtracts and look-up tables. One of these decoders offers the advantage of not requiring the knowledge of the signal-to-noise ratio of the channel, as it usually happens to most of decoders for LDPC codes.

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用FPGA实现两个非常低复杂度的LDPC解码器

低密度奇偶校验(LDPC)码是非常有效的错误控制码，被认为是许多下一代通信系统的一部分。本文介绍了两种低复杂度解码器的FPGA实现。这两种实现操作于任何类型的奇偶校验矩阵(包括随机生成的、结构生成的、系统的或非系统的)，并且可以对任何码率k/n参数化执行。所提出的实现都是非常低的复杂性，因为它们只使用和、减法和查找表进行操作。其中一种解码器的优点是不需要了解信道的信噪比，因为大多数LDPC码的解码器通常都需要了解信道的信噪比。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2011 VII Southern Conference on Programmable Logic (SPL)

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