P. Liao, M. Kuo, C. Tien, Y. -. Chang, P. Hong, T. George, H. Lin, P. W. Li
{"title":"Self-organized gate stack of Ge nanosphere/SiO2/Si1-xGex enables Ge-based monolithically-integrated electronics and photonics on Si platform","authors":"P. Liao, M. Kuo, C. Tien, Y. -. Chang, P. Hong, T. George, H. Lin, P. W. Li","doi":"10.1109/VLSIT.2018.8510695","DOIUrl":null,"url":null,"abstract":"We report the first-of-its-kind, self-organized gate stack of Ge nanosphere (NP) gate/SiO<inf>2</inf>/Si<inf>1-x</inf>Ge<inf>x</inf> channel fabricated in a single oxidation step. Process-controlled tunability of the Ge NP size (5–90nm), SiO<inf>2</inf> thickness (2–4nm), and Ge content (x = 0.65–0.85) and strain engineering (ε<inf>comp</inf> = 1–3%) of the Si<inf>1-x</inf>Ge<inf>x</inf> are achieved. We demonstrated Ge junctionless (JL) n-FETs and photoMOSFETs (PTs) as amplifier and photodetector, respectively, for Ge receivers. L<inf>G</inf> of 75nm JL n-FETs feature I<inf>ON</inf>/I<inf>OFF</inf> > 5×10<sup>8</sup>, I<inf>ON</inf> > 500µA/µm at V<inf>DS</inf> = 1V, T= 80K. Ge-PTs exhibit superior photoresponsivity >1,000A/W and current gain linearity ranging from nW–mW for 850nm illumination. Size-tunable photo-luminescence (PL) of 300–1600nm (NUV-NIR) are observed on 5–100nm Ge NPs. Our gate stack of Ge NP/SiO<inf>2</inf>/Si<inf>1-x</inf>Ge<inf>x</inf> enables a practically achievable building block for monolithically-integrated Ge electronic and photonic ICs (EPICs) on Si.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"520 1","pages":"157-158"},"PeriodicalIF":0.0000,"publicationDate":"2018-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2018.8510695","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
We report the first-of-its-kind, self-organized gate stack of Ge nanosphere (NP) gate/SiO2/Si1-xGex channel fabricated in a single oxidation step. Process-controlled tunability of the Ge NP size (5–90nm), SiO2 thickness (2–4nm), and Ge content (x = 0.65–0.85) and strain engineering (εcomp = 1–3%) of the Si1-xGex are achieved. We demonstrated Ge junctionless (JL) n-FETs and photoMOSFETs (PTs) as amplifier and photodetector, respectively, for Ge receivers. LG of 75nm JL n-FETs feature ION/IOFF > 5×108, ION > 500µA/µm at VDS = 1V, T= 80K. Ge-PTs exhibit superior photoresponsivity >1,000A/W and current gain linearity ranging from nW–mW for 850nm illumination. Size-tunable photo-luminescence (PL) of 300–1600nm (NUV-NIR) are observed on 5–100nm Ge NPs. Our gate stack of Ge NP/SiO2/Si1-xGex enables a practically achievable building block for monolithically-integrated Ge electronic and photonic ICs (EPICs) on Si.