H. Lo, D. Choi, Y. Hu, Y. Shen, Y. Qi, J. Peng, D. Zhou, M. Mohan, C. Yong, H. Zhan, H. Wei, X. He, D. Kang, A. Sirman, Y. Wang, H. Zang, S. Mun, A. Vinslava, W.H. Chen, C. Gaire, J. Liu, X. Dou, Y. Shi, P. Zhao, B. Zhu, A. Jha, X. Zhang, X. Wan, E. Lavigne, C. Kyono, M. Togo, J. Versaggi, H. Yu, O. Hu, J. lee, S. Samavedam, D. K. Sohn
{"title":"A 12nm FinFET Technology Featuring 2nd Generation FinFET for Low Power and High Performance Applications","authors":"H. Lo, D. Choi, Y. Hu, Y. Shen, Y. Qi, J. Peng, D. Zhou, M. Mohan, C. Yong, H. Zhan, H. Wei, X. He, D. Kang, A. Sirman, Y. Wang, H. Zang, S. Mun, A. Vinslava, W.H. Chen, C. Gaire, J. Liu, X. Dou, Y. Shi, P. Zhao, B. Zhu, A. Jha, X. Zhang, X. Wan, E. Lavigne, C. Kyono, M. Togo, J. Versaggi, H. Yu, O. Hu, J. lee, S. Samavedam, D. K. Sohn","doi":"10.1109/VLSIT.2018.8510632","DOIUrl":null,"url":null,"abstract":"We present a state-of-art 12LP FinFET technology with PPA (Performance, Power, and Area) improvement over 14LPP. 12LP enables >10% area reduction including a 7.5T library and 16% power reduction at fixed frequency or a 15% performance improvement at given leakage over 14LPP with comparable reliability and yield. In addition, SRAMs benefit from a 30% leakage reduction at the same Iread. 12LP extends the 14nm technology with compelling performance and area scaling.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"103 1","pages":"215-216"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2018.8510632","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
We present a state-of-art 12LP FinFET technology with PPA (Performance, Power, and Area) improvement over 14LPP. 12LP enables >10% area reduction including a 7.5T library and 16% power reduction at fixed frequency or a 15% performance improvement at given leakage over 14LPP with comparable reliability and yield. In addition, SRAMs benefit from a 30% leakage reduction at the same Iread. 12LP extends the 14nm technology with compelling performance and area scaling.
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