Design Technology Co-Optimization in advanced FDSOI CMOS around the Minimum Energy Point: body biasing and within-cell VT-mixing

Abstract

We propose an original Technology/Design Co-optimization of standard cells mixing devices of different threshold voltages (VT-flavors) within a cell. It is successfully applied with nMOS Low-VT (LVT) and pMOS Super-Low-VT (SLVT) in Ultra-Low-Voltage (ULV) Fully Depleted Silicon-On-Insulator (FDSOI) LETI standard cells using diffusion breaks. It enables adjusting the VT of pMOS subject to SiGe-channel-induced Local Layout Effect (LLE); leading experimentally to a 23% frequency gain on 22nm FDSOI technology for a 2-finger inverter Ring Oscillator (IVSX2 RO) vs. reference LVT at the same static leakage and VDD=0.4V supply voltage; which corresponds to the Minimum Energy Point (MEP). This solution is combined with Forward Body Biasing (FBB), which brings +253% frequency at VDD=0.4V and FBB=1.6V and improves the energy efficiency with a −13% minimum Energy Delay Product (EDP) along with a 50mV VDD reduction at the minimum EDP.