A DDR3 memory based time interleaving FPGA implementation for ISDB-T standard

2011 VII Southern Conference on Programmable Logic (SPL) Pub Date : 2011-04-13 DOI:10.1109/SPL.2011.5782616

E. Marchi, M. Cervetto, Marcelo L. Tenorio

引用次数: 2

Abstract

The ISDB-T standard for digital broadcasting incorporates an extensive signal processing scheme in order to achieve reliable data integrity at the remote receiver. Particularly, the time interleaving stage requires a significant memory depth. Common implementations are often based in single-address access memories, which simplifies the algorithm logic but does not provide a cost-effective solution. This paper presents a DDR3 memory based FPGA implementation of the ISDB-T time interleaving stage. Widely available on the market for a broad type of applications, this kind of memory allows high data throughput and represents a low cost alternative. However, data must comply with a special structure and signalling since the memory access is burst-oriented. Consequently, the complexity is increased. The proposed design is both area-efficient and highly reconfigurable.

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基于DDR3存储器的ISDB-T标准时间交错FPGA实现

用于数字广播的ISDB-T标准包含广泛的信号处理方案，以便在远程接收器上实现可靠的数据完整性。特别是，时间交错阶段需要显著的记忆深度。常见的实现通常基于单地址访问存储器，这简化了算法逻辑，但不提供经济有效的解决方案。本文提出了一种基于DDR3存储器的ISDB-T时间交错级的FPGA实现方法。这种内存在市场上广泛适用于各种类型的应用程序，它允许高数据吞吐量，并且是一种低成本的替代方案。但是，由于内存访问是面向突发的，因此数据必须遵循特殊的结构和信号。因此，复杂性增加了。所提出的设计既具有面积效率又具有高度可重构性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2011 VII Southern Conference on Programmable Logic (SPL)

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