W. Jeong, S. Maeda, H. Lee, Kw. Lee, T.J. Lee, D. Park, Bs Kim, J. Do, T. Fukai, DJ Kwon, KJ Nam, WJ Rim, Minsik Jang, H.T. Kim, YW Lee, Js Park, Ec Lee, DW Ha, C. Park, H. Cho, S.-M. Jung, H. Kang
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引用次数: 26
Abstract
7nm platform technology that takes full advantage of EUV lithography was developed, where EUV was straightforwardly used for single patterning of MOL and BEOL, not just as a means for cutting of SADP/SAQP. The combination of 27nm fin pitch (FP) and 54nm contacted poly pitch (CPP) as well as the high density SRAM cell size of 0.0262 um2 is the smallest in the reported FinFET platform. Further scaling is secured with special constructs and the 3rd generation single diffusion break. Full working of 256M bit SRAM and large-scale logic test chip was demonstrated with guaranteed reliability.
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