A H.264/AVC Quarter-Pixel Motion Estimation Refinement architecture targeting high resolution videos

2011 VII Southern Conference on Programmable Logic (SPL) Pub Date : 2011-04-13 DOI:10.1109/SPL.2011.5782637

M. Corrêa, M. T. Schoenknecht, L. Agostini

引用次数: 3

Abstract

This paper presents a hardware design for the H.264/AVC Quarter-Pixel Motion Estimation Refinement to be used in a complete Fractional Motion Estimation architecture. The architecture was optimized to reach a high throughput through a balanced pipeline and parallelism exploration. The design was described in VHDL and synthesized to an Altera Stratix III FPGA device. The design achieves an operation frequency of 245 MHz, processing up to 39 QHDTV frames (3840×2048 pixels) per second. This architecture is also able to reach real time when processing other resolutions, like HD 1080p (1920×1080 pixels) with lower operation frequencies. The final results are very competitive when compared to related works.

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针对高分辨率视频的H.264/AVC四分之一像素运动估计改进架构

本文提出了H.264/AVC四分之一像素运动估计细化的硬件设计，用于完整的分数阶运动估计体系结构。通过平衡管道和并行性探索，优化了该体系结构以达到高吞吐量。该设计用VHDL语言描述，并合成到Altera Stratix III FPGA器件上。该设计实现了245mhz的工作频率，每秒处理高达39个QHDTV帧(3840×2048像素)。该架构在处理其他分辨率时也能够达到实时性，例如HD 1080p (1920×1080像素)，操作频率较低。与相关作品相比，最终的结果是非常有竞争力的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2011 VII Southern Conference on Programmable Logic (SPL)

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