A highly cost efficient 8F/sup 2/ DRAM cell with a double gate vertical transistor device for 100 nm and beyond

Abstract

This paper describes a highly cost efficient 8F/sup 2/ trench capacitor DRAM cell with a lithography-friendly layout. It consists of only 4 critical masks, i.e. a highly regular trench pattern and three line masks. The cell is shrinkable below 100 nm. It is fabricated with an overlay robust process with a double gate vertical pass transistor in the upper part of the trench capacitor and a double buried strap node contact. The cell features four bitline contacts per cell (two shared with the neighboring cells). Lines of deep oxide isolation trenches provide efficient decoupling of adjacent cells. Feasibility has been demonstrated at a 175 nm design rule with a 128 Mb product chip and a 1 Mb test array at 120 nm.