L. Grenouillet, M. Vinet, J. Gimbert, B. Giraud, J. Noel, Q. Liu, P. Khare, M. Jaud, Y. Le Tiec, R. Wacquez, T. Levin, P. Rivallin, S. Holmes, S. Liu, K. Chen, O. Rozeau, P. Scheiblin, E. Mclellan, M. Malley, J. Guilford, A. Upham, R. Johnson, M. Hargrove, T. Hook, S. Schmitz, S. Mehta, J. Kuss, N. Loubet, S. Teehan, M. Terrizzi, S. Ponoth, K. Cheng, T. Nagumo, A. Khakifirooz, F. Monsieur, P. Kulkarni, R. Conte, J. Demarest, O. Faynot, W. Kleemeier, S. Luning, B. Doris
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引用次数: 61
Abstract
We introduce an innovative dual-depth shallow trench isolation (dual STI) scheme for Ultra Thin Body and BOX (UTBB) FDSOI architecture. Since in the dual STI configuration wells are isolated from one another by the deepest trenches, this architecture enables a full use of the back bias while staying compatible with both standard bulk design and conventional SOI substrates. We demonstrate in 20nm ground rules that we are able to tune Vt by more than 400mV, that transistor performance can be boosted by up to 30% and that Ioff can be controlled over 3 decades by allowing more than VDD/2 to be applied on the back gate.
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