Known-blocking. Synchronization method for reliable processor using TMR & DPR in SRAM FPGAs

2011 VII Southern Conference on Programmable Logic (SPL) Pub Date : 2011-04-13 DOI:10.1109/SPL.2011.5782625

A. Morillo, A. Astarloa, Jesús Lázaro, U. Bidarte, J. Jiménez

引用次数: 3

Abstract

The need of critical applications has derived in the development of several safety techniques that aim to guarantee system operability. The vast majority of these systems own a microprocessor to control its functionality. Thus, system reliability largely depends on the proper function of the microprocessor. In the special case of SRAM FPGAs, Triple Modular Redundancy (TMR) combined with Dynamic Partial Reconfiguration (DPR) allows the development of coarse grain modularity architectures where the redundant module is a soft-core microprocessor or a more complex logical unit based in a processor. However, its main lack is a suitable synchronization method for the faulty module once it is reconfigured. This paper shows the trends on synchronization methods for systems that make use of TMR and DPR and proposes a new synchronization method based on a non blocking scheme.

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Known-blocking。SRAM fpga中基于TMR和DPR的可靠处理器同步方法

为了满足关键应用的需要，开发了几种旨在保证系统可操作性的安全技术。这些系统中的绝大多数都有一个微处理器来控制其功能。因此，系统的可靠性在很大程度上取决于微处理器的正常功能。在SRAM fpga的特殊情况下，三模块冗余(TMR)与动态部分重构(DPR)相结合，允许开发粗粒度模块化架构，其中冗余模块是软核微处理器或基于处理器的更复杂的逻辑单元。然而，它主要缺乏的是一个合适的同步方法，故障模块一旦被重新配置。介绍了基于TMR和DPR的系统同步方法的发展趋势，提出了一种基于无阻塞方案的同步方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2011 VII Southern Conference on Programmable Logic (SPL)

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