Totally silicided (CoSi/sub 2/) polysilicon: a novel approach to very low-resistive gate (/spl sim/2/spl Omega///spl square/) without metal CMP nor etching

Abstract

In this paper we present for the first time mid-gap CoSi/sub 2/ metal gates obtained by total gate silicidation meaning that the silicidation process decay itself once the reaction front arrives down to the gate oxide and no more polysilicon is left. Metal gate are required for FDSOI but they may also be useful for low gate-resistance bulk RF devices. For simplicity, we have investigated totally silicided gates within a 0.1 /spl mu/m CMOS bulk technology. In the next step, CoSi/sub 2/ metal gates were processed after the poly CMP step (first CMP in damascene process) in order to protect source and drain from deep silicidation. Low gate resistivity transistors were obtained, exhibiting good performances without degradation in gate leakage, subthreshold slope nor in drive and off currents compared with reference poly-silicon gate transistors.