P. Coudrain, J. Charbonnier, A. Garnier, P. Vivet, R. Vélard, A. Vinci, F. Ponthenier, A. Farcy, R. Segaud, P. Chausse, L. Arnaud, D. Lattard, E. Guthmuller, G. Romano, A. Gueugnot, F. Berger, J. Beltritti, T. Mourier, M. Gottardi, S. Minoret, C. Ribiére, G. Romero, Pierre-Emile Philip, Y. Exbrayat, D. Scevola, D. Campos, M. Argoud, N. Allouti, R. Eleouet, César Fuguet Tortolero, C. Aumont, D. Dutoit, Corinne Legalland, J. Michailos, S. Chéramy, G. Simon
{"title":"Active Interposer Technology for Chiplet-Based Advanced 3D System Architectures","authors":"P. Coudrain, J. Charbonnier, A. Garnier, P. Vivet, R. Vélard, A. Vinci, F. Ponthenier, A. Farcy, R. Segaud, P. Chausse, L. Arnaud, D. Lattard, E. Guthmuller, G. Romano, A. Gueugnot, F. Berger, J. Beltritti, T. Mourier, M. Gottardi, S. Minoret, C. Ribiére, G. Romero, Pierre-Emile Philip, Y. Exbrayat, D. Scevola, D. Campos, M. Argoud, N. Allouti, R. Eleouet, César Fuguet Tortolero, C. Aumont, D. Dutoit, Corinne Legalland, J. Michailos, S. Chéramy, G. Simon","doi":"10.1109/ECTC.2019.00092","DOIUrl":null,"url":null,"abstract":"We report the first successful technology integration of chiplets on an active silicon interposer, fully processed, packaged and tested. Benefits of chiplet-based architectures are discussed. Built up technology is presented and focused on 3D interconnects process and characterization. 3D packaging is presented up to the successful structural test and characterization of the demonstrator.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"22 1","pages":"569-578"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"37","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2019.00092","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 37
Abstract
We report the first successful technology integration of chiplets on an active silicon interposer, fully processed, packaged and tested. Benefits of chiplet-based architectures are discussed. Built up technology is presented and focused on 3D interconnects process and characterization. 3D packaging is presented up to the successful structural test and characterization of the demonstrator.
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