{"title":"Polylithic Integration of 2.5D and 3D Chiplets Using Interconnect Stitching","authors":"Paul K. Jo, Ting Zheng, M. Bakir","doi":"10.1109/ECTC.2019.00278","DOIUrl":null,"url":null,"abstract":"This paper explores polylithic integration of heterogeneous dice (chiplets) for high-density electronic systems. In this approach, stitch-chips are used to enable 2.5D integration by providing dense signal pathways between assembled 'anchor chips,' while surface-embedded chips provide 3D face-to-face electrical interconnection with corresponding anchor chips. Multi-height Compressible MicroInterconnects (CMIs) are used to enable low-loss and mechanically robust interfaces between the anchor chips and the stitch-chips as well as the surface-embedded chips. Fabrication and assembly of a testbed is reported and demonstrates robust interconnection. In an effort to characterize the CMIs and stitch-chip channels at high-frequency, electromagnetic simulations are carried out and demonstrate less than 0.6 dB insertion loss for 90 µm tall CMIs and 500 µm long channels on a fused silica stitch-chip.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"21 2 1","pages":"1803-1808"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2019.00278","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper explores polylithic integration of heterogeneous dice (chiplets) for high-density electronic systems. In this approach, stitch-chips are used to enable 2.5D integration by providing dense signal pathways between assembled 'anchor chips,' while surface-embedded chips provide 3D face-to-face electrical interconnection with corresponding anchor chips. Multi-height Compressible MicroInterconnects (CMIs) are used to enable low-loss and mechanically robust interfaces between the anchor chips and the stitch-chips as well as the surface-embedded chips. Fabrication and assembly of a testbed is reported and demonstrates robust interconnection. In an effort to characterize the CMIs and stitch-chip channels at high-frequency, electromagnetic simulations are carried out and demonstrate less than 0.6 dB insertion loss for 90 µm tall CMIs and 500 µm long channels on a fused silica stitch-chip.