Yang-Kyu Choi, N. Lindert, Peiqi Xuan, Stephen Tang, Daewon Ha, E. Anderson, T. King, J. Bokor, C. Hu
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引用次数: 213
Abstract
A simplified fabrication process for sub-20 nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET (1999, 2000). Two different patterning approaches-e-beam lithography and spacer lithography-are developed. Selective Ge by LPCVD is utilized to fabricate raised S/D structures which minimize parasitic series resistance and improve drive current.
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