Assessment of the stochastic nature of dielectric breakdown in advanced CMOS technologies utilizing voltage ramp stress methodology

Abstract

The stochastic nature of dielectric breakdown in MG/HK and poly-Si/SiON technologies is investigated. The voltage ramp stress (VRS) methodology was employed to demonstrate that the variability of the Weibull shape parameter, β·(n+1), diminishes with increasing sample size as predicted for a purely stochastic process. However, the V63 confidence limits remain essentially the same and do not follow the predictions of a purely stochastic process. It is suggested that the variability of V63 is limited by the local variations in the oxide thickness for metal gate (MG) / high-K (HK) and poly-Si/SiON technologies.