A 0.13 /spl mu/m high-performance SOI logic technology with embedded DRAM for system-on-a-chip application

Abstract

Reports the successful implementation of a 0.13 /spl mu/m high-performance, silicon-on-insulator (SOI) logic technology to produce a 0.13 /spl mu/m logic-based embedded DRAM (eDRAM) on substrates composed of both bulk Si and SOI or pattern SOI. eDRAM macros are constructed in bulk regions of the wafer and high-performance logic circuits lie on SOI. Pattern SOI wafers are produced by blocking out selected regions of p-type Si wafers from the separation by implantation of oxygen (SIMOX) implant using a thick (> 1 /spl mu/m) hard mask. Test results indicate that SOI eDRAM yield and retention characteristics are comparable to bulk eDRAM. Based on ring oscillator tests, the use of 0.13 /spl mu/m SOI logic devices improves switching speeds by >20% over 0.13 /spl mu/m bulk technology at 1.2 Vdd. These results pave the way for future generations of low power SOI system-on-a-chip (SOC) applications, starting at the 0.1 /spl mu/m node.