Capability evaluation and validation of FC chip scale package structure

Abstract

The requirement of Chip Scale Package (CSP) is growing popular in current 3C industries due to the increasing needs of handheld devices and energy saving. Flip-Chip Chip Scale Package (FCCSP) structure is then designed to meet the small form factor as well as high electrical performance requirements with cost efficiency. The purpose of this study is to evaluate the performance of different kinds of FCCSP structures as FCCSP-A (molding compound with underfill), FCCSP-B (only underfill) and FCCSP-C (only molding compound) structure. Firstly the package warpage performance is compared by using Finite Element Method (FEM). Actual warpage measurements of these three structures are also conducted by the use of shadow moiré methodology for validation. Secondly the die corner stress is compared for the evaluation of package reliability. Thermal performance is also compared and finally the investigation of the solder joint reliability performance by drop test.