Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117216
Sheng-Feng Hsiao, Ming-Kun Chen, Yi-Lung Lin, Yu-Jung Huang, S. Fu
Three dimensions packaging provides a very promising technology for the effective integration of complex systems: devices that are optimally implemented with various different technologies can be separately manufactured and then stacked and connected by means of efficient vertical interconnections over a very short range; this provides most of the benefits of inter-chips for high-bandwidth with a reasonable cost and short development time in the advance of CMOS processes and assembly. This study presents the co-simulation of capacitive coupling pads assignment for the capacitive coupling interconnection. The modelling of a close capacitive coupling interconnection pad is represented by a lumped circuit. The coupling pads of parasitic capacitance are one of the parasitic parameters. The FEM (finite element method) tools simulation results show that the effect of cross-coupling between adjacent channels is dependent on substrate characteristic and pads arrangement. A comparison between simulated and measured circuit performance was shown for a RLC-elements, and qualitative accuracy was obtained. HSPICE tools are applied for the circuit simulations using the equivalent model of coupling pads. Based on the findings of this work, co-simulation methods can reduce simulation time dramatically, the coupling pads assignment can be translated to HSPICE model.
{"title":"Co-simulation of capacitive coupling pads assignment for capacitive coupling interconnection applications","authors":"Sheng-Feng Hsiao, Ming-Kun Chen, Yi-Lung Lin, Yu-Jung Huang, S. Fu","doi":"10.1109/IMPACT.2011.6117216","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117216","url":null,"abstract":"Three dimensions packaging provides a very promising technology for the effective integration of complex systems: devices that are optimally implemented with various different technologies can be separately manufactured and then stacked and connected by means of efficient vertical interconnections over a very short range; this provides most of the benefits of inter-chips for high-bandwidth with a reasonable cost and short development time in the advance of CMOS processes and assembly. This study presents the co-simulation of capacitive coupling pads assignment for the capacitive coupling interconnection. The modelling of a close capacitive coupling interconnection pad is represented by a lumped circuit. The coupling pads of parasitic capacitance are one of the parasitic parameters. The FEM (finite element method) tools simulation results show that the effect of cross-coupling between adjacent channels is dependent on substrate characteristic and pads arrangement. A comparison between simulated and measured circuit performance was shown for a RLC-elements, and qualitative accuracy was obtained. HSPICE tools are applied for the circuit simulations using the equivalent model of coupling pads. Based on the findings of this work, co-simulation methods can reduce simulation time dramatically, the coupling pads assignment can be translated to HSPICE model.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"8 1","pages":"347-350"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72753865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117152
Y. S. Chen, Yang-Sin Lee, Yu-Cheng Lin
This study focuses on examining the resulting stresses of the corner solder ball which is most vulnerable to damage on the flip chip ball grid array (FCBGA) components. A series of tests including thermal cycling, vibration, and highly accelerated life test (HALT) were conducted. Meanwhile, the finite element analysis (FEA) with the commercial ANSYS software was also performed for all the foregoing test conditions. The differences on the resulted strains among the individual thermal cycling, vibration, and HALT test were compared.
{"title":"Comparison among individual thermal cycling, vibration test and the combined test for the life estimation of electronic components","authors":"Y. S. Chen, Yang-Sin Lee, Yu-Cheng Lin","doi":"10.1109/IMPACT.2011.6117152","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117152","url":null,"abstract":"This study focuses on examining the resulting stresses of the corner solder ball which is most vulnerable to damage on the flip chip ball grid array (FCBGA) components. A series of tests including thermal cycling, vibration, and highly accelerated life test (HALT) were conducted. Meanwhile, the finite element analysis (FEA) with the commercial ANSYS software was also performed for all the foregoing test conditions. The differences on the resulted strains among the individual thermal cycling, vibration, and HALT test were compared.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"198 1","pages":"385-388"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73075607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117155
Won Ho Park, Ron McCall, C. K. Yang
Power dissipation and thermal problems have become a growing issue for scaled technology. This phenomenon drives the need for advance cooling systems. It is well-known that cooling the operating temperature results in reduced electric power and/or speed gains. Since cooling cost penalizes the total power, a refrigeration system is developed and experimentally tested to demonstrate that cooling the high performance microprocessor can lead to overall system power improvement. A processor that dissipates 175.4W of maximum power with 30% electronic leakage power operating at 97°C is cooled using our refrigeration system. Measurements show that with a minimum refrigeration COP of 2.7, the processor operates with junction temperature <40°C and offers a 25% total system power reduction over the non-refrigerated design. This experiment is the first demonstration of active cooling that lead reduced total wall power. With an improved compressor that maintains the COP across a broad range of cooling capacity, our analysis shows that at least >13% of total power is saved across the entire range of processor utilization.
{"title":"Total system power minimization of microprocessors using refrigerated systems for electronic cooling","authors":"Won Ho Park, Ron McCall, C. K. Yang","doi":"10.1109/IMPACT.2011.6117155","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117155","url":null,"abstract":"Power dissipation and thermal problems have become a growing issue for scaled technology. This phenomenon drives the need for advance cooling systems. It is well-known that cooling the operating temperature results in reduced electric power and/or speed gains. Since cooling cost penalizes the total power, a refrigeration system is developed and experimentally tested to demonstrate that cooling the high performance microprocessor can lead to overall system power improvement. A processor that dissipates 175.4W of maximum power with 30% electronic leakage power operating at 97°C is cooled using our refrigeration system. Measurements show that with a minimum refrigeration COP of 2.7, the processor operates with junction temperature <40°C and offers a 25% total system power reduction over the non-refrigerated design. This experiment is the first demonstration of active cooling that lead reduced total wall power. With an improved compressor that maintains the COP across a broad range of cooling capacity, our analysis shows that at least >13% of total power is saved across the entire range of processor utilization.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"26 1","pages":"242-245"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85703856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117163
C. Romero, Seungwook Park, Y. Kweon, M. Park
The faster market trend towards smart phones with more advanced computing ability and connectivity will drive the greater need to incorporate more functionality in smaller space by integrating more components and functional blocks into convergent systems in form of chip-level (SOC) or die-level (SIP) packaging. As feature size continues to shrink, it requires combination of stringent design requirements which all interact in order to achieve the desired performance. Also, various limitations will arise in the design of the PCB in terms of size and signal integrity. The substrate or PCB plays critical role in the miniaturization of the overall system and the final application's electrical performance. Given the extreme routing requirement of each component package with high I/O pins and fine pitch area array, the conventional HDI substrate pose some design challenges and limitations. In order to increase the routing density, it often requires smaller trace width and micro via diameter and even the need of adding more metal layers. These, however, will dramatically increase the cost and more reliability risk is expected. In this paper, we present a new generation substrate that could meet the mobile platform requirement by proposing an advanced ultra fine metal resolution substrate. It will demonstrate its high density interconnect capability in a basic 4-layer stack-up structure. One of its advanced features is the ability to adjust board and interconnection impedance in order to optimize signal integrity and more routing capability for dense mobile platform layouts. It will also demonstrate that organic-based substrate may also achieve tighter routing density using limited number of metal layers at smaller and thinner form factor while maintaining the desired signal integrity performance as compared to conventional 8-layer or 10-layer HDI PCBs. Details of electrical simulation and measurement of electrical parameters are also presented and discussed.
{"title":"Advanced high density interconnection substrate for mobile platform application","authors":"C. Romero, Seungwook Park, Y. Kweon, M. Park","doi":"10.1109/IMPACT.2011.6117163","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117163","url":null,"abstract":"The faster market trend towards smart phones with more advanced computing ability and connectivity will drive the greater need to incorporate more functionality in smaller space by integrating more components and functional blocks into convergent systems in form of chip-level (SOC) or die-level (SIP) packaging. As feature size continues to shrink, it requires combination of stringent design requirements which all interact in order to achieve the desired performance. Also, various limitations will arise in the design of the PCB in terms of size and signal integrity. The substrate or PCB plays critical role in the miniaturization of the overall system and the final application's electrical performance. Given the extreme routing requirement of each component package with high I/O pins and fine pitch area array, the conventional HDI substrate pose some design challenges and limitations. In order to increase the routing density, it often requires smaller trace width and micro via diameter and even the need of adding more metal layers. These, however, will dramatically increase the cost and more reliability risk is expected. In this paper, we present a new generation substrate that could meet the mobile platform requirement by proposing an advanced ultra fine metal resolution substrate. It will demonstrate its high density interconnect capability in a basic 4-layer stack-up structure. One of its advanced features is the ability to adjust board and interconnection impedance in order to optimize signal integrity and more routing capability for dense mobile platform layouts. It will also demonstrate that organic-based substrate may also achieve tighter routing density using limited number of metal layers at smaller and thinner form factor while maintaining the desired signal integrity performance as compared to conventional 8-layer or 10-layer HDI PCBs. Details of electrical simulation and measurement of electrical parameters are also presented and discussed.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"130 1","pages":"214-217"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84597129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117154
K. Liu, E. Chen, D. Lee, M. Ma
The requirement of Chip Scale Package (CSP) is growing popular in current 3C industries due to the increasing needs of handheld devices and energy saving. Flip-Chip Chip Scale Package (FCCSP) structure is then designed to meet the small form factor as well as high electrical performance requirements with cost efficiency. The purpose of this study is to evaluate the performance of different kinds of FCCSP structures as FCCSP-A (molding compound with underfill), FCCSP-B (only underfill) and FCCSP-C (only molding compound) structure. Firstly the package warpage performance is compared by using Finite Element Method (FEM). Actual warpage measurements of these three structures are also conducted by the use of shadow moiré methodology for validation. Secondly the die corner stress is compared for the evaluation of package reliability. Thermal performance is also compared and finally the investigation of the solder joint reliability performance by drop test.
{"title":"Capability evaluation and validation of FC chip scale package structure","authors":"K. Liu, E. Chen, D. Lee, M. Ma","doi":"10.1109/IMPACT.2011.6117154","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117154","url":null,"abstract":"The requirement of Chip Scale Package (CSP) is growing popular in current 3C industries due to the increasing needs of handheld devices and energy saving. Flip-Chip Chip Scale Package (FCCSP) structure is then designed to meet the small form factor as well as high electrical performance requirements with cost efficiency. The purpose of this study is to evaluate the performance of different kinds of FCCSP structures as FCCSP-A (molding compound with underfill), FCCSP-B (only underfill) and FCCSP-C (only molding compound) structure. Firstly the package warpage performance is compared by using Finite Element Method (FEM). Actual warpage measurements of these three structures are also conducted by the use of shadow moiré methodology for validation. Secondly the die corner stress is compared for the evaluation of package reliability. Thermal performance is also compared and finally the investigation of the solder joint reliability performance by drop test.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"27 1","pages":"129-132"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87631426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117209
M. Hsieh, Sheng-Tsai Wu, Wei Li, R. Tain, J. Lau, R. Lo, M. Kao
In this investigation, a set of empirical equations which predicts the maximum thermal stresses at the vicinity of a copper filled TSV for 3D IC integration has been proposed. The finite element model of a symmetrical single in-line TSV with redistribution layer has been created at first and the parametric study includes the TSV diameter, pitch, and thickness, and the thickness of SiO2 passivation and Cu seed layer. The methodology of design of experiments (DOE) has been adopted to deliver a set of empirical equations which captures the most important mechanical parameters of TSVs to comprehend the corresponding thermal stress and strain responses. Through this set of empirical equations, the estimated maximum thermal stresses and strains for different TSV diameter (from 10μm to 50μm) can be explained and the significant geometrical parameters can be easily observed. In addition, based on the present parametric study and results, a set of design guidelines for optimizing the mechanical performance of copper filled TSV in 3D IC integration has been proposed. These results are helpful to engineers if thermal stress solutions for TSVs in 3D IC integration are required.
{"title":"Nonlinear thermal stress analyses and design guidelines for through silicon vias (TSVs) in 3D IC integration","authors":"M. Hsieh, Sheng-Tsai Wu, Wei Li, R. Tain, J. Lau, R. Lo, M. Kao","doi":"10.1109/IMPACT.2011.6117209","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117209","url":null,"abstract":"In this investigation, a set of empirical equations which predicts the maximum thermal stresses at the vicinity of a copper filled TSV for 3D IC integration has been proposed. The finite element model of a symmetrical single in-line TSV with redistribution layer has been created at first and the parametric study includes the TSV diameter, pitch, and thickness, and the thickness of SiO2 passivation and Cu seed layer. The methodology of design of experiments (DOE) has been adopted to deliver a set of empirical equations which captures the most important mechanical parameters of TSVs to comprehend the corresponding thermal stress and strain responses. Through this set of empirical equations, the estimated maximum thermal stresses and strains for different TSV diameter (from 10μm to 50μm) can be explained and the significant geometrical parameters can be easily observed. In addition, based on the present parametric study and results, a set of design guidelines for optimizing the mechanical performance of copper filled TSV in 3D IC integration has been proposed. These results are helpful to engineers if thermal stress solutions for TSVs in 3D IC integration are required.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"38 1","pages":"75-78"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86093030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117280
Sheng-Liang Li, Chung-Yen Hsu, Chun-Kai Liu, M. Dai, H. Chien, R. Tain
A novel design for hot spot cooling in 3DIC package by integrating the embedded thermoelectric cooler (ETC) is presented in this paper. The silicon (Si) interposer with through silicon vias (TSVs) was used as electrical paths for ETC and stacked on a Si chip that possesses a hot spot area on it. Finite element analysis (FEA) software ANSYS was utilized in present study to analyze the thermal performance. Three different structures: (1)TEC only, (2)TEC with copper ring and (3)copper spreader only were analyzed in present paper. The first two types are the novel designs and the third one is the traditional structure for thermal management in packaging. The dimensions of the Si chip and Si interposer are 5mm in length and width, and 100um in thickness, respectively. Three different sizes of hot spot area were adopted to investigate the cooling performance of each structure of package. Moreover, Si interposer used as an active device was also discussed. An improved novel design (second type: TEC with copper ring) was demonstrated from simulated results that provide the superior cooling performance to the other two structures.
{"title":"Hot spot cooling in 3DIC package utilizing embedded thermoelectric cooler combined with silicon interposer","authors":"Sheng-Liang Li, Chung-Yen Hsu, Chun-Kai Liu, M. Dai, H. Chien, R. Tain","doi":"10.1109/IMPACT.2011.6117280","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117280","url":null,"abstract":"A novel design for hot spot cooling in 3DIC package by integrating the embedded thermoelectric cooler (ETC) is presented in this paper. The silicon (Si) interposer with through silicon vias (TSVs) was used as electrical paths for ETC and stacked on a Si chip that possesses a hot spot area on it. Finite element analysis (FEA) software ANSYS was utilized in present study to analyze the thermal performance. Three different structures: (1)TEC only, (2)TEC with copper ring and (3)copper spreader only were analyzed in present paper. The first two types are the novel designs and the third one is the traditional structure for thermal management in packaging. The dimensions of the Si chip and Si interposer are 5mm in length and width, and 100um in thickness, respectively. Three different sizes of hot spot area were adopted to investigate the cooling performance of each structure of package. Moreover, Si interposer used as an active device was also discussed. An improved novel design (second type: TEC with copper ring) was demonstrated from simulated results that provide the superior cooling performance to the other two structures.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"798 1","pages":"470-473"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91457949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117252
K. Chung, Chih-Hao Tseng, Liyu Yang
A WLCSP package consists of 2.2 × 2.2 mm2 silicon die, polyimide-based substrate, and 5 × 5 array of solder balls was used as the test vehicle to evaluate its solder joint reliability. Both package level tests with respect to precondition test, temperature cycling test, unbiased highly accelerated stress test (UHAST), and high temperature storage life (HTSL) test and board level tests regarding temperature cycling test have been included in the test plan. Two different lead free solder ball materials (SAC1205 vs. SAC105), under bump metallurgy (Ti/NiV/Cu vs. plated Cu), and die thicknesses (406 μm vs. 356 μm) were assessed. The test results for the package level assessment present that the test vehicle past criteria for all of these required tests. The test results of temperature cycling (−40°C ∼125°C) for the board level assessment show that these controlled variables have unlike performance in the solder joint reliability (SJR) of the WL-CSP package. The SAC105 shows better solder joint reliability performance than that of SAC1205 to provide 13 % improvement in characteristic life (Weibull distribution). The thick die (406 μm) shows statistically better SJR performance than that of thin die (356 μm) to sustain 10% increase in characteristic life (Weibull distribution). On the other hand, standard Ti/NiV/Cu UBM presents statistically equivalent SJR performance as plated Cu in characteristic life. As the results, package design factors of the solder alloy and die thickness play obvious roles in solder joint reliability compared to the factor of UBM. Generally speaking, the WL-CSP package presents appropriate solder joint reliability according to the test results.
采用由2.2 × 2.2 mm2硅芯片、聚酰亚胺基板和5 × 5焊点球阵列组成的WLCSP封装作为测试载体，评估其焊点可靠性。在测试计划中包括了关于前提条件测试、温度循环测试、无偏高加速应力测试(UHAST)和高温储存寿命测试(HTSL)的封装级测试和关于温度循环测试的板级测试。评估了两种不同的无铅焊球材料(SAC1205 vs SAC105)，碰撞冶金(Ti/NiV/Cu vs镀Cu)和模具厚度(406 μm vs 356 μm)。包级评估的测试结果表明，测试车辆通过了所有这些要求测试的标准。电路板水平评估的温度循环(- 40°C ~ 125°C)测试结果表明，这些控制变量在WL-CSP封装的焊点可靠性(SJR)方面具有不同的性能。SAC105表现出比SAC1205更好的焊点可靠性性能，提供了13%的特征寿命提高(威布尔分布)。厚模(406 μm)的SJR性能优于薄模(356 μm)，特征寿命延长10%(威布尔分布)。另一方面，标准Ti/NiV/Cu UBM的SJR性能在特征寿命上与镀Cu相当。结果表明，焊料合金的封装设计因素和模具厚度因素对焊点可靠性的影响明显大于UBM因素。一般来说，根据测试结果，WL-CSP封装具有适当的焊点可靠性。
{"title":"The solder joint reliability assessment of a wafer level CSP package","authors":"K. Chung, Chih-Hao Tseng, Liyu Yang","doi":"10.1109/IMPACT.2011.6117252","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117252","url":null,"abstract":"A WLCSP package consists of 2.2 × 2.2 mm2 silicon die, polyimide-based substrate, and 5 × 5 array of solder balls was used as the test vehicle to evaluate its solder joint reliability. Both package level tests with respect to precondition test, temperature cycling test, unbiased highly accelerated stress test (UHAST), and high temperature storage life (HTSL) test and board level tests regarding temperature cycling test have been included in the test plan. Two different lead free solder ball materials (SAC1205 vs. SAC105), under bump metallurgy (Ti/NiV/Cu vs. plated Cu), and die thicknesses (406 μm vs. 356 μm) were assessed. The test results for the package level assessment present that the test vehicle past criteria for all of these required tests. The test results of temperature cycling (−40°C ∼125°C) for the board level assessment show that these controlled variables have unlike performance in the solder joint reliability (SJR) of the WL-CSP package. The SAC105 shows better solder joint reliability performance than that of SAC1205 to provide 13 % improvement in characteristic life (Weibull distribution). The thick die (406 μm) shows statistically better SJR performance than that of thin die (356 μm) to sustain 10% increase in characteristic life (Weibull distribution). On the other hand, standard Ti/NiV/Cu UBM presents statistically equivalent SJR performance as plated Cu in characteristic life. As the results, package design factors of the solder alloy and die thickness play obvious roles in solder joint reliability compared to the factor of UBM. Generally speaking, the WL-CSP package presents appropriate solder joint reliability according to the test results.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"61 1","pages":"370-372"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80551615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117157
Choupin Huang
Platform clock plays a critical role for digital systems with high-speed serial links. Platform-level reference clock performance analysis is required for all system reference clock architectures to support different platform configurations. The paper presents the advanced platform-level clock jitter and drift methodology being often used by system engineers to guarantee the integrity of platform designs. The best known methods of platform-level clock jitter analysis from the clock sources to receivers due to different jitter characteristics in different clock distribution branches are presented. The novel platform-level cascaded PLL analysis for drift calculation and drift budgeting methodology are introduced.
{"title":"Advanced platform-level clock jitter and drift analysis","authors":"Choupin Huang","doi":"10.1109/IMPACT.2011.6117157","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117157","url":null,"abstract":"Platform clock plays a critical role for digital systems with high-speed serial links. Platform-level reference clock performance analysis is required for all system reference clock architectures to support different platform configurations. The paper presents the advanced platform-level clock jitter and drift methodology being often used by system engineers to guarantee the integrity of platform designs. The best known methods of platform-level clock jitter analysis from the clock sources to receivers due to different jitter characteristics in different clock distribution branches are presented. The novel platform-level cascaded PLL analysis for drift calculation and drift budgeting methodology are introduced.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"51 1","pages":"111-114"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84703033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117166
Mingzhi Dong, Qian Wang, Jian Cai, Jinrui Li, Shuidi Wang
In this paper, performance difference of fine pitch and normal pitch BGA under thermal and mechanical impact conditions has been evaluated by means of thermal shock test as well as board-level drop test. Influence of solder ball material and PCB pad finish was also investigated. The results reveal that decrease of solder ball pitch could lead to increase of vulnerability. Fine pitch BGA fails more rapidly subjected to thermal or mechanical stress. The combination of Sn1.0Ag0.5Cu solder ball and Cu-OSP PCB pad outperformed other testing groups in the research and is recommended for manufacturers. Failure analysis shows that dominant failure mechanism is brittle cracking within or near intermetallics formed between bulk solder and pad metal during soldering reflow process.
{"title":"Reliability of lead-free fine pitch BGA under thermal and mechanical impact","authors":"Mingzhi Dong, Qian Wang, Jian Cai, Jinrui Li, Shuidi Wang","doi":"10.1109/IMPACT.2011.6117166","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117166","url":null,"abstract":"In this paper, performance difference of fine pitch and normal pitch BGA under thermal and mechanical impact conditions has been evaluated by means of thermal shock test as well as board-level drop test. Influence of solder ball material and PCB pad finish was also investigated. The results reveal that decrease of solder ball pitch could lead to increase of vulnerability. Fine pitch BGA fails more rapidly subjected to thermal or mechanical stress. The combination of Sn1.0Ag0.5Cu solder ball and Cu-OSP PCB pad outperformed other testing groups in the research and is recommended for manufacturers. Failure analysis shows that dominant failure mechanism is brittle cracking within or near intermetallics formed between bulk solder and pad metal during soldering reflow process.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"94 1","pages":"67-70"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90862208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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