TingYen Chiang, S. Souri, C. O. Chui, K. C. Saraswat
{"title":"Thermal analysis of heterogeneous 3D ICs with various integration scenarios","authors":"TingYen Chiang, S. Souri, C. O. Chui, K. C. Saraswat","doi":"10.1109/IEDM.2001.979599","DOIUrl":null,"url":null,"abstract":"Presents detailed thermal analysis of high performance three dimensional (3D) ICs under various integration schemes. The model incorporates the effect of vias and power consumption due to both devices in active layers and interconnect joule heating. The results show excellent agreement with the 3D finite element simulations using ANSYS. It is shown that under certain scenarios, 3D ICs can actually lead to better thermal performance than planar (2D) ICs. With the effect of vias, as efficient heat dissipation paths, taken into account, our model provides more realistic temperature rise estimation for 3D ICs. Furthermore, tradeoffs among power, performance, chip real estate and thermal impact for 3D ICs is evaluated. Finally, the thermal influence from incorporating RF circuits and optical interconnect on 3D ICs has been discussed.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"1 1","pages":"31.2.1-31.2.4"},"PeriodicalIF":0.0000,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"115","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2001.979599","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 115
Abstract
Presents detailed thermal analysis of high performance three dimensional (3D) ICs under various integration schemes. The model incorporates the effect of vias and power consumption due to both devices in active layers and interconnect joule heating. The results show excellent agreement with the 3D finite element simulations using ANSYS. It is shown that under certain scenarios, 3D ICs can actually lead to better thermal performance than planar (2D) ICs. With the effect of vias, as efficient heat dissipation paths, taken into account, our model provides more realistic temperature rise estimation for 3D ICs. Furthermore, tradeoffs among power, performance, chip real estate and thermal impact for 3D ICs is evaluated. Finally, the thermal influence from incorporating RF circuits and optical interconnect on 3D ICs has been discussed.