Design innovations to optimize the 3D stackable vertical gate (VG) NAND flash

2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI:10.1109/IEDM.2012.6479015

Chun-Hsiung Hung, H. Lue, Shuo-Nan Hung, C. Hsieh, Kuo-Pin Chang, Ti-Wen Chen, Shih-Lin Huang, Tzung Shen Chen, Chih-Shen Chang, Wen-Wei Yeh, Y. Hsiao, Chieh-Fang Chen, Shih-Cheng Huang, Yan-Ru Chen, Guan-Ru Lee, Chih-Wei Hu, Shih-Hung Chen, C. Chiu, Y. Shih, Chih-Yuan Lu

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引用次数: 8

Abstract

The design architecture for 3D vertical gate (VG) NAND Flash is discussed in detail. With the unique structure of 3D VG and its decoding method, we have developed several important design innovations to optimize this technology: (1) “Shift-BL scramble” to average the BL capacitances, providing uniform CBL's for various memory layers; (2) Optimized read waveforms to suppress the hot-carrier induced read disturb in the page reading mode; (3) Novel reverse read with “multi-Vt sensing technique” for different memory layers to compensate the Vt variation due to the layer-to-layer process difference; (4) Program inhibit method and technique to minimize the “Z-directional” self-boosting program disturb in 3D stackable memory. Optimized chip-level performances with excellent memory window for SLC and MLC operations are demonstrated on a 2-layer 3D VG NAND chip.

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设计创新优化3D可堆叠垂直栅(VG) NAND闪存

详细讨论了三维垂直栅(VG) NAND闪存的设计体系结构。利用3D VG独特的结构和解码方法，我们开发了几项重要的设计创新来优化该技术:(1)“Shift-BL scramble”平均BL电容，为不同的存储层提供统一的CBL;(2)优化了读取波形，抑制了页面读取模式下热载体引起的读取干扰;(3)采用“多Vt感应技术”对不同的记忆层进行反向读取，以补偿由于层与层之间的工艺差异而导致的Vt变化;(4)最小化三维可堆叠存储器中“z向”自增强程序干扰的程序抑制方法和技术。在2层3D VG NAND芯片上展示了具有SLC和MLC操作优良内存窗口的优化芯片级性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2012 International Electron Devices Meeting

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