R. Degraeve, B. Kaczer, F. Schuler, M. Lorenzini, D. Wellekens, P. Hendrickx, J. van Houdt, L. Haspeslagh, G. Tempel, G. Groeseneken
{"title":"Statistical model for stress-induced leakage current and pre-breakdown current jumps in ultra-thin oxide layers","authors":"R. Degraeve, B. Kaczer, F. Schuler, M. Lorenzini, D. Wellekens, P. Hendrickx, J. van Houdt, L. Haspeslagh, G. Tempel, G. Groeseneken","doi":"10.1109/IEDM.2001.979447","DOIUrl":null,"url":null,"abstract":"We present a statistical, unified picture of Stress-Induced Leakage Current (SILC) generation, pre-breakdown current steps and breakdown in 2.4 nm oxide layers during a constant voltage stress. Pre-breakdown current steps were investigated through gate voltage ramp measurements and modeled by means of a percolation model with variable trap-trap distance. During oxide stress, first single-trap conduction paths are formed, followed by two-trap conduction paths which are identified as pre-breakdown current steps in small devices. Finally, a highly conducting path is formed which triggers breakdown.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"1 1","pages":"6.2.1-6.2.4"},"PeriodicalIF":0.0000,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"23","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2001.979447","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 23
Abstract
We present a statistical, unified picture of Stress-Induced Leakage Current (SILC) generation, pre-breakdown current steps and breakdown in 2.4 nm oxide layers during a constant voltage stress. Pre-breakdown current steps were investigated through gate voltage ramp measurements and modeled by means of a percolation model with variable trap-trap distance. During oxide stress, first single-trap conduction paths are formed, followed by two-trap conduction paths which are identified as pre-breakdown current steps in small devices. Finally, a highly conducting path is formed which triggers breakdown.