Customizable security-aware cache for FPGA-based soft processors

2011 VII Southern Conference on Programmable Logic (SPL) Pub Date : 2011-04-13 DOI:10.1109/SPL.2011.5782623

Maciej Kurek, Ioannis Ilkos, W. Luk

引用次数: 1

Abstract

This paper describes a security-aware cache targeting field-programmable gate array (FPGA) technology. Our design is based on an architecture with a remapping table, which provides resilience against side-channel timing attacks. We show how this cache design can be optimised for FPGA resources by an index decoder with content addressable memory structure, which can be customized to meet various requirements. We show, for the first time, how our security-aware cache can be included in the Leon 3 processor, and its performance and resource usage are evaluated.

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基于fpga的软处理器的可定制的安全感知缓存

本文介绍了一种针对现场可编程门阵列(FPGA)的安全感知缓存技术。我们的设计是基于一个具有重新映射表的架构，它提供了抵御侧信道定时攻击的弹性。我们展示了如何通过具有内容可寻址存储器结构的索引解码器优化FPGA资源的缓存设计，该索引解码器可以定制以满足各种要求。我们将首次展示如何将安全感知缓存包含在Leon 3处理器中，并评估其性能和资源使用情况。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2011 VII Southern Conference on Programmable Logic (SPL)

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