Low Temperature Cu Interconnect with Chip to Wafer Hybrid Bonding

Abstract

Current DRAM advanced chip stack packages such as the high bandwidth memory (HBM) use throughsilicon-via (TSV) and thermal compression bonding (TCB) of solder capped micro bumps for the inter-layer connection. The bonding process has low throughput and cannot overcome the challenge of scaling below 40 µm pitch. These are compelling reasons to seek an alternative approach such as hybrid bonding. The pursuit of fine pitch die stacking with TSV interconnect using hybrid bonding is pervasive in the packaging industry today due to the promise of improved performance. Specifically, the Cu interconnect provides improved thermal and electrical performance and the all inorganic interface of the complete die stack offers enhanced thermal-mechanical performance and reliability in the final chip stack. Direct Bond Interconnect technology, also known as low temperature hybrid bonding, forms a spontaneous dielectric-to-dielectric bond at room temperature and then establishes metal-to-metal connection (usually Cu-to-Cu bond) by a low temperature batch annealing process (150 – 300°C). The direct bond process eliminates the need for solder and underfill and associated problems. While the hybrid bonding exists today in wafer-towafer (W2W) format in high volume manufacturing, chip to wafer (C2W) bonding developed for future product lines is making significant process in the past three years. A bonding process with high throughput has been demonstrated with electrical test yield above 90% with a daisy chain structure that covers 50mm^2 of bonding area. The bonded parts showed superior reliability performance in temperature cycling, high temperature storage and autoclave testing. This paper presents the latest development in C2W hybrid bonding and demonstrates the low temperature annealing capability and integration with TSV.