Sheng-Liang Li, Chung-Yen Hsu, Chun-Kai Liu, M. Dai, H. Chien, R. Tain
{"title":"Hot spot cooling in 3DIC package utilizing embedded thermoelectric cooler combined with silicon interposer","authors":"Sheng-Liang Li, Chung-Yen Hsu, Chun-Kai Liu, M. Dai, H. Chien, R. Tain","doi":"10.1109/IMPACT.2011.6117280","DOIUrl":null,"url":null,"abstract":"A novel design for hot spot cooling in 3DIC package by integrating the embedded thermoelectric cooler (ETC) is presented in this paper. The silicon (Si) interposer with through silicon vias (TSVs) was used as electrical paths for ETC and stacked on a Si chip that possesses a hot spot area on it. Finite element analysis (FEA) software ANSYS was utilized in present study to analyze the thermal performance. Three different structures: (1)TEC only, (2)TEC with copper ring and (3)copper spreader only were analyzed in present paper. The first two types are the novel designs and the third one is the traditional structure for thermal management in packaging. The dimensions of the Si chip and Si interposer are 5mm in length and width, and 100um in thickness, respectively. Three different sizes of hot spot area were adopted to investigate the cooling performance of each structure of package. Moreover, Si interposer used as an active device was also discussed. An improved novel design (second type: TEC with copper ring) was demonstrated from simulated results that provide the superior cooling performance to the other two structures.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"798 1","pages":"470-473"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMPACT.2011.6117280","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
A novel design for hot spot cooling in 3DIC package by integrating the embedded thermoelectric cooler (ETC) is presented in this paper. The silicon (Si) interposer with through silicon vias (TSVs) was used as electrical paths for ETC and stacked on a Si chip that possesses a hot spot area on it. Finite element analysis (FEA) software ANSYS was utilized in present study to analyze the thermal performance. Three different structures: (1)TEC only, (2)TEC with copper ring and (3)copper spreader only were analyzed in present paper. The first two types are the novel designs and the third one is the traditional structure for thermal management in packaging. The dimensions of the Si chip and Si interposer are 5mm in length and width, and 100um in thickness, respectively. Three different sizes of hot spot area were adopted to investigate the cooling performance of each structure of package. Moreover, Si interposer used as an active device was also discussed. An improved novel design (second type: TEC with copper ring) was demonstrated from simulated results that provide the superior cooling performance to the other two structures.